Integrated circuit logic functions simulator for selectively connected series of preprogrammed PLA devices using generated sequence of address signals being provided between simulated clock cycles

Claim 2

An IC simulator for simulating logic functions of VLSI integrated circuit hardware according to simulated clock cycles initiated by clock signals, said simulator comprising: data bus means for carrying input and output data signals; a plurality of programmable logic device (PLD) means selectively connected to said data bus means, said plurality of PLD means for executing preprogrammed algorithmic functions on input data signals and providing corresponding output data signals upon receipt of a clock signal for a simulated clock cycle, each of said PLD means being preprogrammed with an algorithmic function corresponding to a logic function of the integrated circuit hardware being simulated, each said PLD means further having an input latch for storing input data signals prior to executing said algorithmic function and an output latch for storing output data signals resulting from said algorithmic function execution, each said output latch corresponding to a real latch within the integrated circuit hardware being simulated; address generator means for providing digital address signals in a sequence, the sequence of said digital address signals being provided between said simulated clock cycles; address bus means for carrying said digital address signals; and a plurality of programmable interconnect logic block (PILB) means connected to said address bus means, each PILB means being connected to a corresponding one of said plurality of PLD means and further being responsive to said digital address signals and preprogrammed for selectively connecting said input and output latches of said corresponding one of said plurality of PLD means to said data bus means, whereby said address generator means controls said plurality of PILB means according to the sequence of said digital address signals to effectuate a corresponding sequence of signal transfer steps in which input and output data signals are transferred from said data bus means to selectively connected input latches or from selectively connected output latches to selectively connected input latches via said data bus means, between said simulated clock cycles.

Claim 3

The IC simulator according to claim 1, wherein said digital address signals comprise multibit address signals.

Claim 4

The IC simulator of claim 1, further comprising monitor means connected to said data bus means for providing, between said simulated clock cycles, input data signals onto said data bus means to input latches selectively connected to said data bus means according to the sequence of said digital address signals, said monitor means further for reading, between said simulated clock cycles, output data signals stored in output latches corresponding to the selectively connected input latches.

Claim 5

The IC simulator according to claim 1, wherein said plurality of PLD means are comprised of programmable logic arrays.

Claim 6

The IC simulator according to claim 1, wherein said plurality of PILB means are comprised of programmable logic arrays.

Claim 7

An IC simulator for simulating logic functions of VLSI integrated circuit hardware according to simulated clock cycles initiated by clock signals, said simulator comprising: a plurality of unit simulator means, each said unit simulator means having: a) data bus means for carrying input and output data signals; b) a plurality of programmable logic device (PLD) means selectively connected to said data bus means, said plurality of PLD means for executing preprogrammed algorithmic functions on input data signals and providing corresponding output data signals upon receipt of a clock signal for a simulated clock cycle, each of said PLD means being preprogrammed with an algorithmic function corresponding to a logic function of the integrated circuit hardware being simulated, each said PLD means further having an input latch for storing input data signals prior to executing said algorithmic function and an output latch for storing output data signals resulting from said algorithmic function execution, each said output latch corresponding to a real latch within the integrated circuit hardware being simulated; c) address generator means for providing digital address signals in a sequence, the sequence of said digital address signals being provided between said simulated clock cycles; d) address bus means for carrying said digital address signals; e) a plurality of programmable interconnect logic block (PILB) means connected to said address bus means, each PILB means being connected to a corresponding one of said plurality of PLD means and further being responsive to said digital address signals and preprogrammed for selectively connecting said input and output latches of said corresponding one of said plurality of PLD means to said data bus means, whereby said address generator means controls said plurality of PILB means according to the sequence of said digital address signals to effectuate a corresponding sequence of signal transfer steps in which input and output data signals are transferred from said data bus means to selectively connected input latches or from selectively connected output latches to selectively connected input latches via said data bus means, between said simulated clock cycles; master data bus means for carrying master data input and output signals; and master controller means for controlling said plurality of unit simulator means to transfer master data input and output signals from said master data bus means to selectively connected input latches of a first unit simulator means or from selectively connected output latches in a first unit simulator means to selectively connected input latches in a second unit simulator means via said master data bus means, between said simulated clock cycles.

Claim 8

An IC simulator for simulating logic functions of VLSI integrated circuit hardware according to simulated clock cycles initiated by clock signals, said simulator comprising: a plurality of unit simulator means, each said unit simulator means having: a) data bus means for carrying input and output data signals; b) a plurality of programmable logic device (PLD) means selectively connected to said data bus means, said plurality of PLD means for executing preprogrammed algorithmic functions on input data signals and providing corresponding output data signals upon receipt of a clock signal for a simulated clock cycle, each of said PLD means being preprogrammed with an algorithmic function corresponding to a logic function of the integrated circuit hardware being simulated, each said PLD means further having an input latch for storing input data signals prior to executing said algorithmic function and an output latch for storing output data signals resulting from said algorithmic function execution, each said output latch corresponding to a real latch within the integrated circuit hardware being simulated; c) address generator means for providing digital address signals in a sequence, the sequence of said digital address signals being provided between said simulated clock cycles; d) address bus means for carrying said digital address signals; e) a plurality of programmable interconnect logic block (PILB) means connected to said address bus means, each PILB means being connected to a corresponding one of said plurality of PLD means and further being responsive to said digital address signals and preprogrammed for selectively connecting said input and output latches of said corresponding one of said plurality of PLD means to said data bus means, whereby said address generator means controls said plurality of PILB means according to the sequence of said digital address signals to effectuate a corresponding sequence of signal transfer steps in which input and output data signals are transferred from said data bus means to selectively connected input latches or from selectively connected output latches to selectively connected input latches via said data bus means, between said simulated clock cycles; master data bus means for carrying master data input and output signals; and master controller means for controlling said plurality of unit simulator means to transfer master data input and output signals from said master data bus means to selectively connected input latches of a first unit simulator means or from selectively connected output latches in a first unit simulator means to selectively connected input latches in a second unit simulator means via said master data bus means, between said simulated clock cycles.