Abstract The present invention provides a semiconductor memory device capable of reducing its current consumption, controlling the generation of noise, and increasing in access using a precharge voltage applied to a precharge circuit. In the semiconductor memory device, a precharge circuit is connected to a pair of data input/output lines, and includes a MOS transistor connected between one of the data input/output lines and a node of a precharge voltage and a MOS transistor connected between the other data input/output line and a node of the precharge voltage. The gates of the MOS transistors are supplied with control signals so that the MOS transistors are turned on when the data input/output lines are precharged. A MOS transistor is connected to the data input/output lines for equalizing them. The precharge voltage is set to half of a value obtained by subtracting the threshold voltage of the MOS transistor from the power supply voltage.
A semiconductor memory device comprising: a pair of data input/output lines; a memory cell circuit including a plurality of cell transistors; a bit line connected to current paths of each of cell transistors of said memory cell circuit; word lines connected to control gates of each of the cell transistors; a sense amplifier for detecting a potential at said bit line corresponding to said memory cell circuit and for outputting a pair of complementary data signals; a pair of column selection MOS transistors connected between said pair of data input/output lines and a pair of output terminals of said sense amplifier; a precharge circuit for precharging said pair of input/output lines with a predetermined potential prior to readout of the potential at said bit line corresponding to said memory cell circuit; and means for applying to said precharge circuit a precharge potential having a value expressed as (VCC-Vth)/2, where VCC is a power supply voltage, and Vth is a threshold voltage of each of said column selection MOS transistors.
Claim 2
Dependent Claim
169 words
A semiconductor memory device comprising: a pair of data input/output lines; a memory cell circuit including a plurality of cell transistors; a bit line connected to current paths of each of cell transistors of said memory cell circuit; word lines connected to control gates of each of the cell transistors; a sense amplifier for detecting a potential at said bit line corresponding to said memory cell circuit and for outputting a pair of complementary data signals; a pair of column selection MOS transistors connected between said pair of data input/output lines and a pair of output terminals of said sense amplifier; a precharge circuit for precharging said pair of input/output lines with a predetermined potential prior to readout of the potential at said bit line corresponding to said memory cell circuit; and means for applying to said precharge circuit a precharge potential having a value expressed as (VCC-Vth)/2, where VCC is a power supply voltage, and Vth is a threshold voltage of each of said column selection MOS transistors.
Claim 3
Dependent Claim
54 words
The semiconductor memory device according to claim 1, wherein said means comprises a MOS transistor, one current path thereof being connected to a power supply, and a series circuit including a first resistor and a second resistor between a current path other than said one current path of said MOS transistor and a ground.