CCD image sensor with photodiodes in a zig-zag pattern and particular transfer gate electrodes formed over channel stop regions and VCCD regions

Claim 1

A CCD image sensor comprising: a plurality of VCCD regions arranged at a constant interval in a horizontal direction with respect to one another, each of the VCCD regions being formed in a zig-zag pattern having a series of curved portions in a vertical direction and being extended to a desired length in the vertical direction; a plurality of groups of first to fourth photodiodes each for generating a signal charge in response to incident light, the first to fourth photodiodes of the respective groups being arranged respectively on the left and right sides of each of said VCCD regions and being isolated from the adjacent VCCD regions via channel stop regions, the first photodiodes being arranged on the left sides of the curved portions of each of said VCCD regions on odd horizontal scanning lines, the second photodiodes being arranged on the right sides of the curved portions of each of said VCCD regions on even horizontal scanning lines, the third photodiodes being arranged on the right sides of the curved portions of each of said VCCD regions on the odd horizontal scanning lines, and the fourth photodiodes being arranged on the left sides of the curved portions of each of said VCCD regions on the even horizontal scanning lines; a HCCD region for transferring in the horizontal direction the signal charges which are transferred from said first to fourth photodiodes through said VCCD regions thereto; a plurality of first transfer gates for connecting said first photodiodes to each of said VCCD regions; a plurality of second transfer gates for connecting said second photodiodes to each of said VCCD regions; a plurality of third transfer gates for connecting said third photodiodes to each of said VCCD regions; a plurality of fourth transfer gates for connecting said fourth photodiodes to each of said VCCD regions; a plurality of first transfer gate electrodes each formed over each of said channel stop regions and each of said VCCD regions, the first transfer gate electrodes being connected respectively to said first transfer gates for application of a first VCCD clock signal; a plurality of second transfer gate electrodes each formed over each of said channel stop regions and each of said VCCD regions, the second transfer gate electrodes being connected respectively to said third transfer gates for application of a second VCCD clock signal; a plurality of third transfer gate electrodes each formed over each of said channel stop regions and each of said VCCD regions, the third transfer gate electrodes being connected respectively to said fourth transfer gates for application of a third VCCD clock signal; and a plurality of fourth transfer gate electrodes each formed over each of said channel stop regions and each of said VCCD regions, the fourth transfer gate electrodes being connected respectively to said second transfer gates for application of a fourth VCCD clock signal.