Method for performing a split read/write operation in a dynamic random access memory

Claim 1

A method for performing operations in a monolithic memory device having a plurality of circuit banks of memory cells, the method comprising the following steps: a) writing first data to at least one of said plurality of circuit banks; b) reading second data from at least one of said plurality of circuit banks; and c) reading from at least one of said plurality of circuit banks while substantially simultaneously writing to at least one of said plurality of circuit banks and communicating said first and second data to and from said plurality of circuit banks through an external port in a single memory cycle.

Claim 2

A method for performing operations in a monolithic memory device having a plurality of circuit banks of memory cells, the method comprising the following steps: a) writing first data to at least one of said plurality of circuit banks; b) reading second data from at least one of said plurality of circuit banks; and c) reading from at least one of said plurality of circuit banks while substantially simultaneously writing to at least one of said plurality of circuit banks and communicating said first and second data to and from said plurality of circuit banks through an external port in a single memory cycle.

Claim 6

A method for performing a write operation to a first bank of memory cells of a monolithic memory chip and for performing a read operation to a second bank of memory cells of the monolithic memory chip in a single memory cycle, comprising: a) disabling digit lien equilibration circuitry in said first bank and disabling digit line equilibration circuitry in said second bank; b) selecting a memory cell in said first bank and selecting a memory cell in said second bank; c) activating a row line coupled to said selected memory cell in said first bank and activating a row line coupled to said selected memory cell in said second bank; d) transferring charge stored in said selected memory cell to digit lines in said first bank and transferring charge stored in said selected memory cells to digit lines in said second bank; e) activating an n sense amplifier in order to amplify said charge transferred to said digit lines in said first bank and activating an n sense amplifier in order to amplify said charge transferred to said digit lines in said second bank; f) disabling Input/Output line equilibrate circuitry in said first bank; g) activating a write diver in said first bank; h) activating a column decoder access device, said activating allowing said write driver to overwrite said charge on said digit lines in said first bank; i) activating a p sense amplifier for amplifying data to be written to said selected memory cells in said first bank; j) activating a p sense amplifier in said second bank; k) disabling a write driver in said second bank; l) activating said DC sense amplifier in said second bank; m) activating a column decoder access device in said second bank; n) disabling equilibrate circuitry to a DC sense amplifier in said second bank; and o) enabling an output buffer to allow said amplified charge to be driven from said digit lines to an output pin through said DC sense amplifier in said second bank.

Claim 7

A method for performing a write operation to a first bank of memory cells of a monolithic memory chip and for performing a read operation to a second bank of memory cells of the monolithic memory chip in a single memory cycle, comprising: a) disabling digit lien equilibration circuitry in said first bank and disabling digit line equilibration circuitry in said second bank; b) selecting a memory cell in said first bank and selecting a memory cell in said second bank; c) activating a row line coupled to said selected memory cell in said first bank and activating a row line coupled to said selected memory cell in said second bank; d) transferring charge stored in said selected memory cell to digit lines in said first bank and transferring charge stored in said selected memory cells to digit lines in said second bank; e) activating an n sense amplifier in order to amplify said charge transferred to said digit lines in said first bank and activating an n sense amplifier in order to amplify said charge transferred to said digit lines in said second bank; f) disabling Input/Output line equilibrate circuitry in said first bank; g) activating a write diver in said first bank; h) activating a column decoder access device, said activating allowing said write driver to overwrite said charge on said digit lines in said first bank; i) activating a p sense amplifier for amplifying data to be written to said selected memory cells in said first bank; j) activating a p sense amplifier in said second bank; k) disabling a write driver in said second bank; l) activating said DC sense amplifier in said second bank; m) activating a column decoder access device in said second bank; n) disabling equilibrate circuitry to a DC sense amplifier in said second bank; and o) enabling an output buffer to allow said amplified charge to be driven from said digit lines to an output pin through said DC sense amplifier in said second bank.

Claim 9

A method for performing memory operations in a single memory cycle in a monolithic random access memory device having a first bank and a second bank, comprising the following steps: a) providing a first write enable signal; b) providing a second write enable signal; c) providing an output enable signal; d) writing to the first bank when the first write enable signal is active; e) writing to the second bank when the second write enable signal is active; f) reading from the first bank when the first write enable signal is inactive and the output enable signal is active; and g) reading from the second bank when the second write enable signal is inactive and the output enable signal is active, wherein the method allows said output enable signal to be active when one of said first and said second write enable signals are active.

Claim 10

A method for performing memory operations in a single memory cycle in a monolithic random access memory device having a first bank and a second bank, comprising the following steps: a) providing a first write enable signal; b) providing a second write enable signal; c) providing an output enable signal; d) writing to the first bank when the first write enable signal is active; e) writing to the second bank when the second write enable signal is active; f) reading from the first bank when the first write enable signal is inactive and the output enable signal is active; and g) reading from the second bank when the second write enable signal is inactive and the output enable signal is active, wherein the method allows said output enable signal to be active when one of said first and said second write enable signals are active.

Claim 22

A method for performing a memory operation in a single memory cycle in a monolithic memory chip having a first memory bank and a second memory bank, comprising: a) writing input data to said first memory bank from an output port; b) substantially simultaneously reading output data from said second memory bank at said output port; and c) refreshing stored data in a memory of said second memory bank.

Claim 23

A method for performing a memory operation in a single memory cycle in a monolithic memory chip having a first memory bank and a second memory bank, comprising: a) writing input data to said first memory bank from an output port; b) substantially simultaneously reading output data from said second memory bank at said output port; and c) refreshing stored data in a memory of said second memory bank.