US5281548A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Plug-based floating gate memory
Assignee: Micron Technology Inc
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Filing: 1992-07-28
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Granted: 1994-01-25
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Expires: 2012-07-28
Abstract
Abstract A device and a method of forming a floating gate memory transistor of very small area, thereby allowing a high-density integrated circuit chip, more specifically for Erasable Programmable Read-Only Memory (EPROM) or similar non-volatile devices. In a first embodiment, a method is disclosed that fabricates a programmable memory cell described as a "diffusion cut" cell where a plug-type floating gate contact hole cuts through a diffusion region and partially into a substrate region. In a second embodiment, a method is disclosed that fabricates a programmable memory cell described as an "oxide cut" cell, where the plug-type floating gate contact hole only penetrates a silicon oxide layer. This "oxide cut" cell is formed in a similar fashion except penetration does not go into the diffusion region or substrate.
Inventors
- 👤 Kirk D. Prall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:48
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
298 words
A method of fabricating a minimum area floating gate memory cell within an IC chip contact well comprising the steps of: a. growing and patterning a field oxide on a substrate by a LOCOS process; b. implanting an impurity element in the substrate to form a diffusion region adjacent the field oxide; c. depositing an oxide layer over the diffusion region and field oxide; d. patterning and etching a contact well in the oxide layer, field oxide, diffusion region, and substrate further comprising: i. performing a cell plug masking; ii. etching the oxide layer; iii. etching the silicon and diffusion region, thereby forming an extended channel; e. growing a gate/tunnel oxide layer within the contact well; f. depositing and doping a first polysilicon layer with the contact well, thereby forming a floating gate and capacitor C1; g. etching the first polysilicon layer until the only polysilicon is within the contact well forming a polysilicon plug; h. depositing a second polysilicon layer within the contact well; i. etching back the second polysilicon layer leaving a thin layer of the second polysilicon on a perimeter of the contact well; j. depositing an ONO dielectric layer over the second polysilicon layer wherein the ONO dielectric layer is about 100 Å thick; k. depositing and doping a third polysilicon layer over the contact hole, thereby forming a second capacitor C2 between the third polysilicon layer and the second polysilicon layer wherein a capacitance ratio of C2/C1 is maximized by controlling a depth of the oxide layer of step c, thereby providing a maximum voltage and charge on the floating gate during electrical programming; l. depositing a tungsten silicide layer over the third polysilicon layer; and then m. masking and etching the third polysilicon layer and tungsten silicide to form a word line.
Claim 2
Independent Claim
298 words
A method of fabricating a minimum area floating gate memory cell within an IC chip contact well comprising the steps of: a. growing and patterning a field oxide on a substrate by a LOCOS process; b. implanting an impurity element in the substrate to form a diffusion region adjacent the field oxide; c. depositing an oxide layer over the diffusion region and field oxide; d. patterning and etching a contact well in the oxide layer, field oxide, diffusion region, and substrate further comprising: i. performing a cell plug masking; ii. etching the oxide layer; iii. etching the silicon and diffusion region, thereby forming an extended channel; e. growing a gate/tunnel oxide layer within the contact well; f. depositing and doping a first polysilicon layer with the contact well, thereby forming a floating gate and capacitor C1; g. etching the first polysilicon layer until the only polysilicon is within the contact well forming a polysilicon plug; h. depositing a second polysilicon layer within the contact well; i. etching back the second polysilicon layer leaving a thin layer of the second polysilicon on a perimeter of the contact well; j. depositing an ONO dielectric layer over the second polysilicon layer wherein the ONO dielectric layer is about 100 Å thick; k. depositing and doping a third polysilicon layer over the contact hole, thereby forming a second capacitor C2 between the third polysilicon layer and the second polysilicon layer wherein a capacitance ratio of C2/C1 is maximized by controlling a depth of the oxide layer of step c, thereby providing a maximum voltage and charge on the floating gate during electrical programming; l. depositing a tungsten silicide layer over the third polysilicon layer; and then m. masking and etching the third polysilicon layer and tungsten silicide to form a word line.
Claim 3
Independent Claim
293 words
A method of fabricating a minimum area floating gate memory cell within an IC chip contact well comprising the steps of: a. growing and patterning a field oxide on a substrate by a LOCOS process; b. implanting an impurity element in the substrate to form a diffusion region adjacent the field oxide; c. depositing an oxide layer over the diffusion region and field oxide; d. patterning and etching a contact well in the oxide layer further comprising: i. performing a cell plug masking; ii. etching the oxide layer; iii. etching the silicon and diffusion region, thereby forming an extended channel; e. growing a gate/tunnel oxide layer within the contact well, thereby forming a floating gate and a capacitor C1 between the first polysilicon layer and the substrate, said capacitor C1 having a minimal capacitance; f. depositing and doping a first polysilicon layer within the contact well, thereby forming a floating gate and capacitor C1; g. etching the first polysilicon layer until the only polysilicon is within the contact well forming a polysilicon plug; h. depositing a second polysilicon layer within the contact well; i. etching back the second polysilicon layer leaving a thin layer of the second polysilicon on a perimeter of the contact well; j. depositing an ONO dielectric layer over the second polysilicon layer wherein the ONO dielectric layer is about 100 Å thick; k. depositing and doping a third polysilicon layer over the contact hole, thereby forming a second capacitor C2 between the third polysilicon layer and the second polysilicon layer C2 having a larger capacitance than C1; l. depositing a tungsten silicide layer over the third polysilicon layer; and then m. masking and etching the third polysilicon layer and tungsten silicide to form a control gate and word line.
Claim 4
Independent Claim
293 words
A method of fabricating a minimum area floating gate memory cell within an IC chip contact well comprising the steps of: a. growing and patterning a field oxide on a substrate by a LOCOS process; b. implanting an impurity element in the substrate to form a diffusion region adjacent the field oxide; c. depositing an oxide layer over the diffusion region and field oxide; d. patterning and etching a contact well in the oxide layer further comprising: i. performing a cell plug masking; ii. etching the oxide layer; iii. etching the silicon and diffusion region, thereby forming an extended channel; e. growing a gate/tunnel oxide layer within the contact well, thereby forming a floating gate and a capacitor C1 between the first polysilicon layer and the substrate, said capacitor C1 having a minimal capacitance; f. depositing and doping a first polysilicon layer within the contact well, thereby forming a floating gate and capacitor C1; g. etching the first polysilicon layer until the only polysilicon is within the contact well forming a polysilicon plug; h. depositing a second polysilicon layer within the contact well; i. etching back the second polysilicon layer leaving a thin layer of the second polysilicon on a perimeter of the contact well; j. depositing an ONO dielectric layer over the second polysilicon layer wherein the ONO dielectric layer is about 100 Å thick; k. depositing and doping a third polysilicon layer over the contact hole, thereby forming a second capacitor C2 between the third polysilicon layer and the second polysilicon layer C2 having a larger capacitance than C1; l. depositing a tungsten silicide layer over the third polysilicon layer; and then m. masking and etching the third polysilicon layer and tungsten silicide to form a control gate and word line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-24 | 1997-07-26 | 1998-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-24 | 2001-07-26 | 2002-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-24 | 2005-07-26 | 2006-01-25 | $7700.00 | Window Closed / Lapsed |