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US5286607A
Expired / Lapsed
US
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Bi-layer resist process for semiconductor processing
Assignee: GlobalFoundries Singapore Pte Ltd
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Filing: 1991-12-09
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Granted: 1994-02-15
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Expires: 2011-12-09
Abstract
Abstract A multi-level patterning process for use in the semiconductor fabrication technology that will consistently produce a very fine and well defined pattern, and which can be re-worked, especially at the early stages of the process is accomplished. In the process, a thick resist, such as a Novolak resin with suitable additives is spun on a wafer. This material is heavily dyed to the exposing wave length of the radiant energy source of the stepper. The planerizing layer is exposed to a silicon containing atmosphere, such as hexamethyldisilazane (HMDS) for a period of time and a temperature sufficient for the silicon to penetrate a short distance, for example about 0.25 micrometers into the resist. The resist is crosslinked during this bake or during a subsequent bake. These wafers are now ready for standard resist processing. The resist is spun, exposed, and developed. The wafers are then inspected for error. Rework can be accomplished at the stage by stripping the top resist and recoating. After inspection, the wafers go through a short RIE that transfers the pattern down through the silicon containing layer. This etch is then converted to an oxygen gas only etch that etches the rest of the way through the planerizing layer. The silicon containing resist layer acts as an etch mask. The wafer has now completed the lithography step and is ready for further processing.
Inventors
- 👤 Andrew V. Brown
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:03
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/004; G03F7/09; G03F7/094; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/95
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
218 words
An improved process for forming a patterned masking layer having a desired pattern of areas on the top surface of a semiconductor wafer using a multi-level resist system comprising: forming on the top surface of said wafer a planarizing first layer of an organic polymer that is reactive with an organic silane compound; exposing said first layer to a silicon containing medium for a period of time and at a temperature sufficient to cause partial penetration of silicon into said first layer; depositing a resist layer over the first layer, exposing the resist layer to the desired pattern, and developing the resist layer to expose areas of said first layer that define said desired pattern; exposing the wafer of a reactive ion etching environment for a time sufficient to partially remove the exposed areas of said first layer including the silicon that penetrated the first layer; exposing the wafer to further reactive ion etching with an oxygen plasma in which the resist layer is eroded away to expose the silicon in the first layer which is then converted to silicon oxide by reaction with the oxygen plasma; and continuing the reactive ion etching in an oxygen plasma wherein the silicon oxide protects the first layer regions, but allow unprotected areas defining said desired pattern to be eroded away.
Claim 2
Dependent Claim
218 words
An improved process for forming a patterned masking layer having a desired pattern of areas on the top surface of a semiconductor wafer using a multi-level resist system comprising: forming on the top surface of said wafer a planarizing first layer of an organic polymer that is reactive with an organic silane compound; exposing said first layer to a silicon containing medium for a period of time and at a temperature sufficient to cause partial penetration of silicon into said first layer; depositing a resist layer over the first layer, exposing the resist layer to the desired pattern, and developing the resist layer to expose areas of said first layer that define said desired pattern; exposing the wafer of a reactive ion etching environment for a time sufficient to partially remove the exposed areas of said first layer including the silicon that penetrated the first layer; exposing the wafer to further reactive ion etching with an oxygen plasma in which the resist layer is eroded away to expose the silicon in the first layer which is then converted to silicon oxide by reaction with the oxygen plasma; and continuing the reactive ion etching in an oxygen plasma wherein the silicon oxide protects the first layer regions, but allow unprotected areas defining said desired pattern to be eroded away.
Claim 3
Dependent Claim
33 words
The method of claim 1 wherein said organic polymer of said first layer is a material selected from the group consisting of Novolak resins, polyphenol resins, polyepoxide resins, polyvinyl alcohol, and mixtures thereof.
Claim 4
Dependent Claim
22 words
The method of claim 2 wherein the thickness of said first layer is in the range of about 0.8 to 3.0 micrometers.
Claim 5
Dependent Claim
21 words
The method of claim 2 wherein the thickness of said first layer is in the range of 0.8 to 1.5 micrometers.
Claim 6
Dependent Claim
18 words
The method of claim 2 wherein a dye is embodied in said first layer, the dye is antireflective.
Claim 7
Dependent Claim
11 words
The method of claim 5 wherein said dye is a benzylphenone.
Claim 8
Dependent Claim
25 words
The method of claim 5 wherein said silicon containing medium is selected from the group consisting of hexamethyldisilazane, tetramethyldisilazane, bisaminosiloxane, hexamethyl cyclotrisilazane and mixtures thereof.
Claim 9
Dependent Claim
41 words
The method of claim 7 wherein the time of exposure of said first layer to said silicon containing medium is the range of about 5 to 300 seconds and at a temperature in the range of about 60° to 200° C.
Claim 10
Dependent Claim
27 words
The method of claim 8 wherein the wafer, following exposure to a silicon containing medium, is baked to further cross link the material of said first layer.
Claim 11
Dependent Claim
26 words
The method of claim 8 wherein the depth of penetration of silicon into said first layer is in the range of about 0.1 to 0.5 micrometers.
Claim 12
Dependent Claim
28 words
The method of claim 10 wherein the initial ion etching environment to remove the top layer portion of said first layer, including the silicon, includes CHF 3 .
Claim 13
Dependent Claim
29 words
The method of claim 11 wherein the exposure time of the wafer to the initial reactive ion etching environment is in the range of about 5 to 120 seconds.
Claim 14
Dependent Claim
21 words
The method of claim 8 wherein the thickness of said resist is in the range of about 0.8 to 1.5 micrometers.
Claim 15
Dependent Claim
224 words
An improved process for forming a patterned masking layer having a desired pattern on the top surface of a semiconductor wafer using a multi-level resist system comprising: forming on the top surface of said wafer a planarizing first layer of an organic polymer that is reactive with an organic silane compound; exposing said first layer to a hexamethyldisilizane medium for a period of time and at a temperature sufficient to cause partial penetration of silicon into said first layer in the range of about 0.1 to 0.5 micrometers; depositing a resist layer over the first layer, exposing the resist layer to the desired pattern, and developing the resist layer to expose areas of said first layer that define said desired pattern; exposing the wafer to a reactive ion etching environment for a time sufficient to partially remove the exposed areas of said first layer including the silicon that penetrated the first layer; exposing the wafer to further reactive ion etching with an oxygen plasma in which the resist layer is eroded away to expose the silicon in the first layer which is then converted to silicon oxide by reaction with the oxygen plasma; and continuing the reactive ion etching in an oxygen plasma wherein the silicon oxide protects the first layer regions, but allow unprotected areas defining said desired patterns to be eroded away.
Claim 16
Dependent Claim
224 words
An improved process for forming a patterned masking layer having a desired pattern on the top surface of a semiconductor wafer using a multi-level resist system comprising: forming on the top surface of said wafer a planarizing first layer of an organic polymer that is reactive with an organic silane compound; exposing said first layer to a hexamethyldisilizane medium for a period of time and at a temperature sufficient to cause partial penetration of silicon into said first layer in the range of about 0.1 to 0.5 micrometers; depositing a resist layer over the first layer, exposing the resist layer to the desired pattern, and developing the resist layer to expose areas of said first layer that define said desired pattern; exposing the wafer to a reactive ion etching environment for a time sufficient to partially remove the exposed areas of said first layer including the silicon that penetrated the first layer; exposing the wafer to further reactive ion etching with an oxygen plasma in which the resist layer is eroded away to expose the silicon in the first layer which is then converted to silicon oxide by reaction with the oxygen plasma; and continuing the reactive ion etching in an oxygen plasma wherein the silicon oxide protects the first layer regions, but allow unprotected areas defining said desired patterns to be eroded away.
Claim 17
Dependent Claim
33 words
The method of claim 14 wherein said organic polymer of said first layer is a material selected from the group consisting of Novolak resin, polyphenol resin, polyepoxide resin, polyvinyl alcohol, and mixtures thereof.
Claim 18
Dependent Claim
22 words
The method of claim 15 wherein the thickness of said first layer is in the range of about 0.8 to 3.0 micrometers.
Claim 19
Dependent Claim
40 words
The method of claim 14 wherein time of exposure of said first layer to said silicon containing medium is the range of about 50 to 200 seconds and at a temperature in the range of about 60° to 200° C.
Claim 20
Dependent Claim
27 words
The method of claim 17 wherein the wafer, following exposure to a silicon containing medium, is baked to further cross link the material of said first layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |