US5289026A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Asymmetric floating gate overlap for improved device characteristics in buried bit-line devices
Assignee: Intel Corp
•
Filing: 1991-08-14
•
Granted: 1994-02-22
•
Expires: 2011-08-14
Abstract
Abstract An electrically erasable non-volatile EPROM memory device having an asymmetric floating gate with respect to a buried source region and a buried drain region is disclosed. A patterned floating gate member is formed over a portion of the source region and a portion of the drain region producing a floating gate-to-source overlap and a floating gate-to-drain overlap, respectively, such that the floating gate-to-source overlap is less than the floating gate-to-drain overlap.
Inventors
- 👤 Tong-Chern Ong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:45
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/6891; H10B; H10B69/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
122 words
An array of electrically erasable non-volatile memory devices comprising: a monocrystalline silicon layer including a plurality of buried source regions and a plurality of buried drain regions, said source regions and said drain regions alternating and spaced apart, wherein said drain regions are shared by adjacent ones of said memory devices in said array; wherein each of said memory devices comprises: field oxide areas over the source region and the drain region; a floating gate member overlapping a portion of the source region and a portion of the drain region forming a floating gate-to-source overlap and a floating gate-to-drain overlap, respectively, such that the floating gate-to-source overlap is less than the floating gate-to-drain overlap; an insulating layer; and a control gate member.
Claim 2
Dependent Claim
122 words
An array of electrically erasable non-volatile memory devices comprising: a monocrystalline silicon layer including a plurality of buried source regions and a plurality of buried drain regions, said source regions and said drain regions alternating and spaced apart, wherein said drain regions are shared by adjacent ones of said memory devices in said array; wherein each of said memory devices comprises: field oxide areas over the source region and the drain region; a floating gate member overlapping a portion of the source region and a portion of the drain region forming a floating gate-to-source overlap and a floating gate-to-drain overlap, respectively, such that the floating gate-to-source overlap is less than the floating gate-to-drain overlap; an insulating layer; and a control gate member.
Claim 3
Dependent Claim
17 words
The device of claim 1, wherein the floating gate-to-drain overlap is no greater than about 0.9 μm.
Claim 4
Dependent Claim
17 words
The device of claim 2, wherein the floating gate-to-source overlap is no greater than about 0.5 μm.
Claim 5
Dependent Claim
20 words
The device of claim 3, wherein the floating gate member is between about 1200 Å and about 2000 Å thick.
Claim 6
Dependent Claim
16 words
The device of claim 1 wherein the floating gate-to-source overlap is no greater than about 0.5μ.
Claim 7
Dependent Claim
26 words
The device of claim 1 wherein floating gate-to-drain overlap is between approximately 0.5μ and 0.9μ and the floating gate-to-source overlap is between approximately 0.1μ and 0.5μ.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-21 | 1997-08-23 | 1998-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-21 | 2001-08-23 | 2002-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-21 | 2005-08-23 | 2006-02-22 | $7700.00 | Window Closed / Lapsed |