US5289027A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ultrathin submicron MOSFET with intrinsic channel
Assignee: Raytheon Co
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Filing: 1992-09-28
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Granted: 1994-02-22
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Expires: 2012-09-28
Abstract
Abstract A submicron MOSFET is fabricated on an ultrathin layer with a generally intrinsic channel having a dopant concentration less than about 10 16 cm -3 . The channel thickness is preferably no greater than about 0.2 microns; the ratio of channel thickness to length is less than about 1:4, and preferably no greater than about 1:2. Punchthrough and other short-channel effects are inhibited by the application of an appropriate back-gate voltage, which may also be varied to adjust the voltage threshold.
Inventors
- 👤 Kyle W. Terrill
- 👤 Prahalad K. Vasudev
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:06
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
158 words
A metal-oxide-semiconductor field transistor (MOSFET) structure, comprising: a first insulating layer, the thickness of said first insulating layer being within the approximate range of 0.3-0.5 microns, a submicron-thick semiconductor layer on said first insulating layer, said semiconductor layer having mutually spaced doped source and drain regions and a generally intrinsic bulk channel region of bulk semiconductor material extending between said source and drain regions, said channel region having a dopant concentration less than about 10 16 cm -3 , a second insulating layer on said channel region, a conductive gate on said insulating layer, and means for applying a back-gate bias voltage to induce both charge carriers in the channel region for MOSFET operation, and an electric field in the channel region for restricting punchthrough and other short-channel effects, said means for applying a back-gate bias voltage comprising a semiconductor substrate for said first insulating layer, and a conductive electrode on said substrate for receiving a voltage signal.
Claim 2
Dependent Claim
158 words
A metal-oxide-semiconductor field transistor (MOSFET) structure, comprising: a first insulating layer, the thickness of said first insulating layer being within the approximate range of 0.3-0.5 microns, a submicron-thick semiconductor layer on said first insulating layer, said semiconductor layer having mutually spaced doped source and drain regions and a generally intrinsic bulk channel region of bulk semiconductor material extending between said source and drain regions, said channel region having a dopant concentration less than about 10 16 cm -3 , a second insulating layer on said channel region, a conductive gate on said insulating layer, and means for applying a back-gate bias voltage to induce both charge carriers in the channel region for MOSFET operation, and an electric field in the channel region for restricting punchthrough and other short-channel effects, said means for applying a back-gate bias voltage comprising a semiconductor substrate for said first insulating layer, and a conductive electrode on said substrate for receiving a voltage signal.
References Cited (Backward Citations)
US3821781A
Cited
US4236167A
Cited
US4420870A
Cited
US4823180A
Cited
US4499482A
Cited
US4555623A
Cited
US4748485A
Cited
EP0211367A2
Cited
JPS63151083A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-21 | 1997-08-23 | 1998-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-21 | 2001-08-23 | 2002-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-21 | 2005-08-23 | 2006-02-22 | $7700.00 | Window Closed / Lapsed |