Semiconductor memory having one-transistor/one-capacitor memory cells and having both improved noise ratio and high density integration

Claim 2

A semiconductor memory, comprising: a plurality of word lines; a plurality of data lines disposed so as to intersect said plurality of word lines; memory cells each consisting of one transistor and one capacitor and disposed at given cross-points between said plurality or word lines and said plurality of data lines; a dummy data line provided in common to said plurality of data lines; a plurality of dummy cells disposed at given cross-points between said plurality of word lines and said dummy data line for generating a reference signal; signal converting means connected electrically to said plurality of data lines, respectively, and to said dummy data line; and differential signal detecting means provided for said plurality of data lines, respectively; wherein said signal converting means associated with each of said plurality of data lines has an output electrically connected to one of differential inputs of said differential signal detecting means, and wherein said signal converting means, associated with said dummy data line, has an output which is electrically connected to another of the differential inputs of said differential signal detecting means.

Claim 3

A semiconductor memory according to claim 1, wherein said dummy data line is interposed between two adjacent ones of said plurality of data lines.

Claim 4

A semiconductor memory according to claim 1, wherein said signal converting means comprises plural signal converting circuits provided for said plurality of data lines and said dummy data line, respectively, and wherein said differential signal detecting means comprises plural differential signal detecting circuits corresponding in number to the number of data lines in said plurality of data lines, each differential signal detecting circuit having a first input coupled to an output of a signal converting circuit and having a second input coupled to the output of that one of said plurality of signal converting circuits associated with said dummy data line.

Claim 5

A semiconductor memory according to claim 3, wherein the signal converting circuit provided for said dummy data line includes a pair of signal converters disposed at both ends of said dummy data line, respectively.

Claim 6

A semiconductor memory according to claim 1, wherein said signal converting means is comprised of a voltage-to-current converter circuit and a current-to-voltage converter circuit coupled thereto.

Claim 7

A semiconductor memory, comprising: a plurality of global data lines; a global dummy data line provided in common to said plurality of global data lines; first signal converting means connected to each of said plurality of global data lines; second signal converting means connected to said global dummy data line; differential signal detecting means provided at each of said plurality of global data lines; a plurality of memory blocks, each memory block comprising: a plurality of word lines, a plurality of data lines disposed so as to intersect said plurality of word lines, memory cells each including one transistor and one capacitor and disposed at given cross-points between said plurality of word lines and said plurality of data lines, a dummy data line provided in common to said plurality of data lines, a plurality of dummy cells disposed at given cross-points between said plurality of word lines and said dummy data line for generating a reference signal, third signal converting means coupled to said plurality of data lines and said plurality of global data lines, and fourth signal converting means connected to said dummy data line and said global dummy data line; wherein said first signal converting means associated with each of said plurality of global data lines has an output electrically connected to one of differential inputs of said differential signal detecting means; and wherein said second signal converting means has an output electrically connected to another of the differential inputs of said differential signal detecting means.

Claim 8

A semiconductor memory, comprising: a plurality of global data lines; a global dummy data line provided in common to said plurality of global data lines; first signal converting means connected to each of said plurality of global data lines; second signal converting means connected to said global dummy data line; differential signal detecting means provided at each of said plurality of global data lines; a plurality of memory blocks, each memory block comprising: a plurality of word lines, a plurality of data lines disposed so as to intersect said plurality of word lines, memory cells each including one transistor and one capacitor and disposed at given cross-points between said plurality of word lines and said plurality of data lines, a dummy data line provided in common to said plurality of data lines, a plurality of dummy cells disposed at given cross-points between said plurality of word lines and said dummy data line for generating a reference signal, third signal converting means coupled to said plurality of data lines and said plurality of global data lines, and fourth signal converting means connected to said dummy data line and said global dummy data line; wherein said first signal converting means associated with each of said plurality of global data lines has an output electrically connected to one of differential inputs of said differential signal detecting means; and wherein said second signal converting means has an output electrically connected to another of the differential inputs of said differential signal detecting means.

Claim 9

A semiconductor memory according to claim 6, wherein said global dummy line is interposed between the adjacent ones of said plurality of global data lines.

Claim 10

A semiconductor memory according to claim 6, wherein said global data lines are disposed in parallel and are arranged as first and second groups of global data lines, said first group of global data lines includes each one of alternating ones of the parallel disposed data lines and said second group of global data lines includes each one of alternating ones of data lines other than those included in said first group, wherein each first signal converting circuit and differential signal sensing circuit associated with said first group of global data lines are provided at first ends of the data global lines of said first group, respectively, and wherein each first signal converting circuit and differential signal sensing circuit associated with said second group of global data lines are provided at second ends of the global data lines of said second group, respectively, said second ends respectively correspond to ends on the global data lines, of both said first and second groups, opposing from that of said first ends thereof.

Claim 11

A semiconductor memory according to claim 8, wherein said second signal converting means provided for said global dummy data line includes a pair of signal converters disposed at both ends of said global dummy data line, respectively.

Claim 12

A semiconductor memory according to claim 1, wherein an electrode contacted to an impurity-doped region of a transistor constituting said memory cell is extended over said transistor and said data line to thereby constitute a capacitor of said memory cell in cooperation with an insulation film provided over said impurity-doped region and a conductive electrode provided on said impurity-doped region.

Claim 13

A semiconductor memory according to claim 3, wherein said plurality of data lines are disposed in parallel and are arranged as first and second groups of data lines, said first group of data lines includes each one of alternating ones of the parallel disposed data lines and said second group of data lines includes each one of alternating ones of data lines other than those included in said first group, wherein each signal converting circuit and differential signal detecting circuit associated with said first group of data lines are provided at first ends of the data lines of said first group, respectively, and wherein each signal converting circuit and differential signal detecting circuit associated with said second group of data lines are provided at second ends of the data lines of said second group, respectively, said second ends respectively correspond to ends on the data lines of both said first and second groups opposing from that of said first ends thereof.

Claim 14

A semiconductor memory according to claim 3, wherein each of said plurality of signal converting circuits is comprised of a series arrangement of a voltage-to-current converter and a current-to-voltage converter.

Claim 15

A semiconductor memory according to claim 6, wherein said first signal converting means comprises plural first signal converters provided for said global data lines, respectively, wherein said second signal converting means comprises a second signal converter, and wherein said differential signal signal detecting means comprises plural differential signal sensing circuits corresponding in number to the number of global data lines in said plurality of global data lines, each sensing circuit having a first input coupled to an output of a first signal converter and having a second input coupled to an output of said second signal converter.

Claim 16

A semiconductor memory, comprising: a plurality of global data lines; a global dummy data line provided in common to said plurality of global data lines; first signal converting means connected to each of said plurality of global data lines; second signal converting means connected to said global dummy data line; differential signal detecting means provided at each of said plurality of global data lines; a plurality of m emory blocks, each memory block comprising: a plurality of word lines, a plurality of data lines disposed so as to intersect said plurality of word lines, memory cells each including one transistor and one capacitor and disposed at given cross-points between said plurality of word lines and said plurality of data lines, a plurality of dummy data lines provided in common to said plurality of data lines, a plurality of dummy cells disposed at given cross-points between said plurality of word lines and said plurality of dummy data lines for generating a reference signal, third signal converting means provided in common to individual groups of data lines, respectively, and connected to, a plurality of first switch means for connecting said third signal converting means to said plurality of data lines, fourth signal converting means provided in common to said plurality of dummy data lines and electrically connected to said global dummy data line, and second switch means for electrically connecting said fourth signal converting means to said plurality of dummy data lines; wherein said first signal converting means associated with each of said plurality of global data lines has an output electrically connected to one of differential inputs of said differential signal detecting means, and wherein said second signal converting means has an output electrically connected to another of the differential inputs of said differential signal detecting means.

Claim 17

A semiconductor memory, comprising: a plurality of global data lines; a global dummy data line provided in common to said plurality of global data lines; first signal converting means connected to each of said plurality of global data lines; second signal converting means connected to said global dummy data line; differential signal detecting means provided at each of said plurality of global data lines; a plurality of m emory blocks, each memory block comprising: a plurality of word lines, a plurality of data lines disposed so as to intersect said plurality of word lines, memory cells each including one transistor and one capacitor and disposed at given cross-points between said plurality of word lines and said plurality of data lines, a plurality of dummy data lines provided in common to said plurality of data lines, a plurality of dummy cells disposed at given cross-points between said plurality of word lines and said plurality of dummy data lines for generating a reference signal, third signal converting means provided in common to individual groups of data lines, respectively, and connected to, a plurality of first switch means for connecting said third signal converting means to said plurality of data lines, fourth signal converting means provided in common to said plurality of dummy data lines and electrically connected to said global dummy data line, and second switch means for electrically connecting said fourth signal converting means to said plurality of dummy data lines; wherein said first signal converting means associated with each of said plurality of global data lines has an output electrically connected to one of differential inputs of said differential signal detecting means, and wherein said second signal converting means has an output electrically connected to another of the differential inputs of said differential signal detecting means.

Claim 18

A semiconductor memory according to claim 14, wherein said first signal converting means comprises plural first signal converters provided for said global data lines, respectively, wherein said second signal converting means comprises a second signal converter, and wherein said differential signal detecting means comprises plural differential signal sensing circuits corresponding in number to the number of global data lines in said plurality of global data lines, each sensing circuit having a first input coupled to an output of a first signal converter and having a second input coupled to an output of said second signal converter.

Claim 19

A semiconductor memory according to claim 15, wherein said third signal converting means comprises plural third signal converters, commonly provided for said groups of data lines, respectively, and wherein said fourth signal converting means comprises a fourth signal converter.

Claim 20

A semiconductor memory according to claim 16, wherein said first and second signal converters are current-to-voltage converters, respectively, and wherein said third and fourth signal converters are voltage-to-current converters.

Claim 21

A semiconductor memory according to claim 8, wherein each said first signal converting circuit is a current-to-voltage converter.

Claim 22

A semiconductor memory according to claim 15, wherein said global data lines are disposed in parallel and are arranged as first and second groups of global data lines, said first group of global data lines includes each one of alternating ones of the parallel disposed global data lines and said second group of global data lines includes each one of alternating ones of global data lines other than those included in said first group, wherein each first signal converting circuit and differential signal sensing circuit associated with said first group of global data lines are provided at first ends of the data global lines of said first group, respectively, and wherein each first signal converting circuit and differential signal sensing circuit associated with said second group of global data lines are provided at second ends of the global data lines of said second group, respectively, said second ends respectively correspond to ends on the global data lines, of both said first and second groups, opposing from that of said first ends thereof.