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US5313432A
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Segmented, multiple-decoder memory array and method for programming a memory array
Assignee: Texas Instruments Inc
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Filing: 1991-11-12
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Granted: 1994-05-17
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Expires: 2011-11-12
Abstract
Abstract A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.
Inventors
- 👤 Sung-Wei Lin
- 👤 John F. Schreck
- 👤 Phat C. Truong
- 👤 David J. McElroy
- 👤 Harvey J. Stiegler
- 👤 Benjamin H. Ashmore, Jr.
- 👤 Manzur Gill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:37
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/06; G11C16/08; G11C16/10; G11C16/12; G11C5/00; G11C5/02; G11C5/025; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
288 words
A memory array comprising a plurality of segments of memory cells, each segment including a plurality of memory cells arranged in rows and columns, each memory cell including a control electrode, a first electrode, a second electrode, and a current path between the first and second electrodes; a plurality of wordlines, control electrodes of memory cells in the same row being connected to a respective one of said wordlines; a plurality of source-column lines, first electrodes of memory cells in the same column being connected to a corresponding one of said source-column lines; a plurality of drain-column lines, second electrodes of memory cells in the same column being connected to an associated one of said drain-column lines; a first wordline decoder circuit for selecting and accessing said wordlines; a drain-column decoder circuit for selecting and accessing said drain-column lines, said drain-column decoder circuit having a plurality of output terminals; a driven source supply for supplying electric potentials to said source-column lines, said driven source supply having at least one output terminal; a segment-select decoder circuit having a drain-select terminal and a source-select terminal; a first logic switch connected between each source-column line and said at least one output terminal of said driven source supply, each first logic switch having a control electrode, each control electrode of each first logic switch in the same segment being connected to said source-select terminal of said segment-select decoder circuit; a second logic switch connected between each drain-column line and one of said plurality of output terminals of said drain-column decoder circuit, each second logic switch having a control electrode, each control electrode of each second logic switch in the same segment being connected to said drain-select terminal of said segment-select decoder circuit.
Claim 2
Dependent Claim
288 words
A memory array comprising a plurality of segments of memory cells, each segment including a plurality of memory cells arranged in rows and columns, each memory cell including a control electrode, a first electrode, a second electrode, and a current path between the first and second electrodes; a plurality of wordlines, control electrodes of memory cells in the same row being connected to a respective one of said wordlines; a plurality of source-column lines, first electrodes of memory cells in the same column being connected to a corresponding one of said source-column lines; a plurality of drain-column lines, second electrodes of memory cells in the same column being connected to an associated one of said drain-column lines; a first wordline decoder circuit for selecting and accessing said wordlines; a drain-column decoder circuit for selecting and accessing said drain-column lines, said drain-column decoder circuit having a plurality of output terminals; a driven source supply for supplying electric potentials to said source-column lines, said driven source supply having at least one output terminal; a segment-select decoder circuit having a drain-select terminal and a source-select terminal; a first logic switch connected between each source-column line and said at least one output terminal of said driven source supply, each first logic switch having a control electrode, each control electrode of each first logic switch in the same segment being connected to said source-select terminal of said segment-select decoder circuit; a second logic switch connected between each drain-column line and one of said plurality of output terminals of said drain-column decoder circuit, each second logic switch having a control electrode, each control electrode of each second logic switch in the same segment being connected to said drain-select terminal of said segment-select decoder circuit.
Claim 3
Dependent Claim
23 words
The memory array of claim 1, wherein each wordline of each segment is connected to a wordline of at least one other segment.
Claim 4
Dependent Claim
25 words
The memory array of claim 1, wherein each drain-column line of each segment is connected to a drain-column line of at least one other segment.
Claim 5
Dependent Claim
28 words
The memory array of claim 1, wherein said segments are arranged in columns, and wherein said segment-select decoder circuit is located adjacent one of said columns of segments.
Claim 6
Dependent Claim
23 words
The memory array of claim 1, wherein said first wordline decoder circuit selects and accesses said wordlines during reading of said memory cells.
Claim 7
Dependent Claim
46 words
The memory array of claim 1, wherein said first wordline decoder circuit selects and accesses said wordlines during reading of said memory cells and wherein said first wordline decoder circuit includes identical subcircuits, each of said subcircuits being connected to at least one of said segments.
Claim 8
Dependent Claim
46 words
The memory array of claim 1, wherein said first wordline decider circuit selects and accesses said wordlines during reading of said memory cells and wherein said memory array includes a second wordline decoder circuit that selects and accesses said wordlines during programming of said memory cells.
Claim 9
Dependent Claim
61 words
The memory array of claim 1, wherein said first wordline decoder circuit selects and accesses said wordlines during reading of said memory cells, wherein said memory array includes a second wordline decoder circuit that selects and accesses said wordlines during programming of said memory cells, and wherein said first wordline decoder circuit and said second wordline decoder circuit are located separately.
Claim 10
Dependent Claim
87 words
The memory array of claim 1, wherein said segments are arranged in columns, wherein said first wordline decoder circuit selects and accesses said wordlines during reading of said memory cells, wherein said memory array includes a second wordline decoder circuit that selects and accesses said wordlines during programming of said memory cells, and wherein said first wordline decoder circuit is located at one end of said columns of segments and wherein said second wordline decoder circuit is located at the other end of said columns of segments.
Claim 11
Dependent Claim
33 words
The memory array of claim 1, wherein each first logic switch is a field-effect transistor and each control electrode of each first logic switch is a control-gate terminal of a corresponding field-effect transistor.
Claim 12
Dependent Claim
50 words
The memory array of claim 1, wherein each first logic switch is a field-effect transistor located at one end of each source-column line, wherein each source-column line is a buried diffusion, and wherein a source and a drain of each field-effect transistor are buried diffusions incorporated in each source-column-line diffusion.
Claim 13
Dependent Claim
34 words
The memory array of claim 1, wherein each second logic switch is a field-effect transistor and wherein each control electrode of each second logic switch is a control-gate terminal of a corresponding field-effect transistor.
Claim 14
Dependent Claim
50 words
The memory array of claim 1, wherein each second logic switch is a field-effect transistor located at one end of each drain-column line, wherein each drain-column line is a buried diffusion, and wherein a source and a drain of each field-effect transistor are buried diffusions incorporated in each drain-column-line diffusion.
Claim 15
Dependent Claim
274 words
A non-volatile memory array comprising: a drain-column decoder having a plurality of output terminals; a driven source supply having at least one output terminal; a segment-select circuit having a source-select signal terminal and having a drain-select signal terminal; a first wordline-decoder circuit having a plurality of output terminals; a plurality of rows and columns of segments, each segment including: a plurality of memory cells arranged in rows and columns, each memory cell including a control electrode, a first electrode, a second electrode, and a current path between said first and second electrodes; a plurality of wordlines, each wordline connected to control electrodes of memory cells in a respective row of memory cells and each wordline connected to a corresponding one of said output terminals of said first wordline decoder circuit; a plurality of source-column lines and a plurality of drain-column lines, each source-column line connected to the first electrode of each memory cell in an associated column of said memory cells and each drain-column line connected to the second electrode of each memory cell in an associated column of said memory cells; first logic switches respectively connecting each source-column line to said terminal of said driven source supply, each first logic switch having a control electrode, each control electrode of each first logic switch being connected to said source-selected signal terminal of said segment select circuit; and second logic switches respectively connecting each drain-column line to a corresponding one of said terminals of said drain-column decoder, each second logic switch having a control electrode, each control electrode of each second logic switch being connected to said drain-select signal terminal of said segment select circuit.
Claim 16
Dependent Claim
274 words
A non-volatile memory array comprising: a drain-column decoder having a plurality of output terminals; a driven source supply having at least one output terminal; a segment-select circuit having a source-select signal terminal and having a drain-select signal terminal; a first wordline-decoder circuit having a plurality of output terminals; a plurality of rows and columns of segments, each segment including: a plurality of memory cells arranged in rows and columns, each memory cell including a control electrode, a first electrode, a second electrode, and a current path between said first and second electrodes; a plurality of wordlines, each wordline connected to control electrodes of memory cells in a respective row of memory cells and each wordline connected to a corresponding one of said output terminals of said first wordline decoder circuit; a plurality of source-column lines and a plurality of drain-column lines, each source-column line connected to the first electrode of each memory cell in an associated column of said memory cells and each drain-column line connected to the second electrode of each memory cell in an associated column of said memory cells; first logic switches respectively connecting each source-column line to said terminal of said driven source supply, each first logic switch having a control electrode, each control electrode of each first logic switch being connected to said source-selected signal terminal of said segment select circuit; and second logic switches respectively connecting each drain-column line to a corresponding one of said terminals of said drain-column decoder, each second logic switch having a control electrode, each control electrode of each second logic switch being connected to said drain-select signal terminal of said segment select circuit.
Claim 17
Dependent Claim
23 words
The memory array of claim 14, wherein each wordline of a segment is connected to a wordline of at least one other segment.
Claim 18
Dependent Claim
25 words
The memory array of claim 14, wherein each drain-column line of each segment is connected to a drain-column line of at least one other segment.
Claim 19
Dependent Claim
28 words
The memory array of claim 14, wherein said segments are arranged in columns, and wherein said segment-select decoder circuit is located adjacent one of said columns of segment.
Claim 20
Dependent Claim
21 words
The memory array of claim 14, wherein said first wordline-decoder circuit selects and accesses said wordlines for reading said memory cells.
Claim 21
Dependent Claim
45 words
The memory array of claim 14, wherein said first wordline-decoder circuit selects and accesses said wordlines for reading said memory cells and wherein said first wordline-decoder circuit includes identical subcircuits, each of said subcircuits connected to at least one wordline of one of said segments.
Claim 22
Dependent Claim
48 words
The memory array of claim 14, wherein said first wordline-decoder circuit selects and accesses said wordlines for reading said memory cells and wherein said memory array includes a second wordline-decoder circuit that selects and accesses said wordlines for at least one of programming and erasing said memory cells.
Claim 23
Dependent Claim
62 words
The memory array of claim 14, wherein said first wordline-decoder circuit selects and accesses said wordlines for reading said memory cells, wherein said memory array includes a second wordline-decoder circuit that selects and accesses said wordlines for at least one of programming and erasing said memory cells, and wherein said first wordline decoder circuit and said second wordline decoder circuit are separated.
Claim 24
Dependent Claim
82 words
The memory array of claim 14, wherein said segment ar arranged in columns, wherein said first wordline-decoder circuit selects and accesses said wordlines for reading said memory cells, wherein said memory array includes a second wordline-decoder circuit that functions to select and access said wordlines for programming said memory cells, wherein said first wordline-decoder circuit is located at one end of said columns of segments, and wherein said second wordline-decoder circuit is located at the other end of said columns of segment.
Claim 25
Dependent Claim
33 words
The memory array of claim 14, wherein each first logic switch is a field-effect transistor and the control electrode of each first logic switch is a control-gate terminal of a corresponding field-effect transistor.
Claim 26
Dependent Claim
50 words
The memory array of claim 14, wherein each first logic switch is a field-effect transistor located at one end of each source-column line, wherein each source-column line is a buried diffusion, and wherein a source and a drain of each field-effect transistor are buried diffusions incorporated in each source-column-line diffusion.
Claim 27
Dependent Claim
35 words
The memory array of claim 14, wherein each second logic switch is a field-effect transistor and wherein the control electrode of each second logic switch is a control gate terminal of a corresponding field-effect transistor.
Claim 28
Dependent Claim
50 words
The memory array of claim 14, wherein each second logic switch is a field-effect transistor located at one end of each drain-column line, wherein each drain-column line is a buried diffusion, and wherein a source and a drain of each field-effect transistor are buried diffusions incorporated in each drain-column-line diffusion.
Claim 29
Independent Claim
245 words
A method for programming a memory array including segments of nonvolatile memory cells, each segment having source-column lines, wordlines and drain-column lines, said memory cells arranged in rows and columns, each memory cell having a first electrode, a second electrode, a part of a semiconductor substrate between the first and second electrodes, a control electrode, a floating gate conductor insulated from and located between the control electrode and said part of said semiconductor substrate, a tunneling window between the first electrode and the floating gate, each control electrode connected to a wordline of said memory array, each first electrode connected to one of said source-column lines, each second electrode connected to one of said drain-column lines, the method comprising: placing a first voltage on all of the source-column lines of a non-selected segment; placing said first voltage on all of the drain-column lines of said non-selected segment; allowing all of said source-column lines of a selected segment of said memory array to electrically float; placing a second voltage on a selected wordline of said selected segment; and placing a third voltage on a selected drain-column line of said selected segment; the difference in voltage between said second voltage and said third voltage being sufficient to cause electrons to migrate across the tunneling window of a memory cell connected to said selected wordline and said selected drain-column line to program that memory cell, said first voltage being intermediate to said second voltage and said third voltage.
Claim 30
Independent Claim
245 words
A method for programming a memory array including segments of nonvolatile memory cells, each segment having source-column lines, wordlines and drain-column lines, said memory cells arranged in rows and columns, each memory cell having a first electrode, a second electrode, a part of a semiconductor substrate between the first and second electrodes, a control electrode, a floating gate conductor insulated from and located between the control electrode and said part of said semiconductor substrate, a tunneling window between the first electrode and the floating gate, each control electrode connected to a wordline of said memory array, each first electrode connected to one of said source-column lines, each second electrode connected to one of said drain-column lines, the method comprising: placing a first voltage on all of the source-column lines of a non-selected segment; placing said first voltage on all of the drain-column lines of said non-selected segment; allowing all of said source-column lines of a selected segment of said memory array to electrically float; placing a second voltage on a selected wordline of said selected segment; and placing a third voltage on a selected drain-column line of said selected segment; the difference in voltage between said second voltage and said third voltage being sufficient to cause electrons to migrate across the tunneling window of a memory cell connected to said selected wordline and said selected drain-column line to program that memory cell, said first voltage being intermediate to said second voltage and said third voltage.
Claim 31
Dependent Claim
19 words
The method of claim 27, wherein said second voltage is applied to said selected wordline in a gradual manner.
Claim 32
Dependent Claim
26 words
The method of claim 27, wherein a voltage intermediate to said second voltage and said third voltage is applied to nonselected wordlines of said memory array.
Claim 33
Dependent Claim
48 words
The method of claim 27, wherein said array includes at least one latch circuit connected to one of said drain-column lines, wherein said third voltage is stored in said at lest one latch circuit and wherein more than one memory cell in said selected segment is programmed simultaneously.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-16 | 1997-11-15 | 1998-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-16 | 2001-11-15 | 2002-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-16 | 2005-11-15 | 2006-05-17 | $7700.00 | Window Closed / Lapsed |