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US5315558A
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Integrated circuit memory with non-binary array configuration
Assignee: NXP BV
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Filing: 1993-04-21
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Granted: 1994-05-24
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Expires: 2013-04-21
Abstract
Abstract Memory arrays of non-binary physical dimensions are disclosed. A novel addressing scheme provides that multiple word lines are activated in response to each received address code. Generally, at least two physical block rows containing blocks of an addressed logical block row are activated in response to each address. Block rows containing redundant blocks are activated in response to every address. In a specific embodiment, a 1 M-bit array arranged in 11 rows of blocks and 6 columns of blocks functions as an 8×8 block logical array, with two blocks available for redundancy. The availability of non-binary physical arrays affords a designer new flexibility in meeting packaging constraints and redundancy specifications.
Inventors
- 👤 Ejaz U. Hag
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:09
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
264 words
A memory device comprising: an array of memory cells arranged in blocks, said blocks being arranged in P physical block rows and Q physical block columns, where 2 M <P<2 M+1 and 2 N <Q<2 N+1 , where M, N, P and Q are integers, said memory cells being arranged in array cell rows and array cell columns, the cells in each of said blocks being arranged in block cell rows and block cell columns, each of said block cell rows being the intersection of a respective array cell row and a respective block, each of said block cell columns being the intersection of a respective physical array cell column and a respective block; data port means for communication between said memory cells and a host system; address input means for receiving address codes; and address decoding means for decoding said address codes so as to select at least one of said cells for communication with said host system for each of said address codes, said address decoding means including word line decoding means for selecting at least one of said array cell rows, said address decoding means including block decoding means for selecting at least one block so as to select the block cell row at the intersection of said array cell row and said block, said address decoding means including column decoding means selecting block cell columns of said at least one block; whereby the at least one cell at the intersection of said selected block cell row and said selected block cell column is selected for communication with said host system.
Claim 2
Dependent Claim
264 words
A memory device comprising: an array of memory cells arranged in blocks, said blocks being arranged in P physical block rows and Q physical block columns, where 2 M <P<2 M+1 and 2 N <Q<2 N+1 , where M, N, P and Q are integers, said memory cells being arranged in array cell rows and array cell columns, the cells in each of said blocks being arranged in block cell rows and block cell columns, each of said block cell rows being the intersection of a respective array cell row and a respective block, each of said block cell columns being the intersection of a respective physical array cell column and a respective block; data port means for communication between said memory cells and a host system; address input means for receiving address codes; and address decoding means for decoding said address codes so as to select at least one of said cells for communication with said host system for each of said address codes, said address decoding means including word line decoding means for selecting at least one of said array cell rows, said address decoding means including block decoding means for selecting at least one block so as to select the block cell row at the intersection of said array cell row and said block, said address decoding means including column decoding means selecting block cell columns of said at least one block; whereby the at least one cell at the intersection of said selected block cell row and said selected block cell column is selected for communication with said host system.
Claim 3
Dependent Claim
13 words
A device as recited in claim 1 wherein 2 S <P·Q, where S=M+N+1.
Claim 4
Dependent Claim
12 words
A device as recited in claim 2 wherein P·Q<2 T where T=M+N+1.2.
Claim 5
Dependent Claim
73 words
A memory device as recited in claim 2 wherein said address decoding means defines a logical array of 2 M logical block rows and 2 N+1 logical block columns, said logical array including 2 S of said blocks, said word line decoding means having row activation means for activating a physical cell row in each physical block row containing a block included in a logical block row selected by a given address code.
Claim 6
Dependent Claim
49 words
A memory device as recited in claim 4 wherein said physical array includes at least one redundant block which is not included in said logical array, said row activation means activating at least one physical cell row in said redundant block in response to at least one address code.
Claim 7
Dependent Claim
30 words
A memory device as recited in claim 4 wherein said blocks include R redundant blocks not included in said logical array where R is an integer and 2 S +R=P·Q.
Claim 8
Dependent Claim
26 words
A memory device as recited in claim 6 wherein all of said redundant blocks are included within a first block row of said P block rows.
Claim 9
Dependent Claim
62 words
A memory device as recited in claim 7 wherein said word line decoding means selects at least a first and a second of said physical array cell rows in response to at least some of said address codes, said first block row containing said first array cell row and a second of said P block rows containing said second array cell row.
Claim 10
Dependent Claim
49 words
A memory device as recited in claim 6 wherein said P block rows and Q block columns constitute a P+Q element set, all of said redundant blocks are included within one element of said set, said one element also including at least two blocks included in said logical array.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-23 | 1997-11-22 | 1998-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-23 | 2001-11-22 | 2002-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-23 | 2005-11-22 | 2006-05-24 | $7700.00 | Window Closed / Lapsed |