Reprogrammable interconnect architecture using fewer storage cells than switches

Claim 2

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors; an I by J array of N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors, where I, J, and N are integers and I+J is greater than 2, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; decoder means having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, and wherein the state of each control signal is a function of the state of the M inputs of said decoder means.

Claim 3

The user re-programmable interconnect architecture of claim 1 wherein a selected state of the M inputs of said decoder means causes each control signal from said decoder means to assume said off state.

Claim 4

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; decoder means having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, wherein the state of each control signal is a function of the state of the M inputs of said decoder means, a selected state of the M inputs of said decoder means causes each control signal from said decoder means to assume said off state, and wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and said decoder means comprises a one of N decoder circuit.

Claim 5

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; decoder means having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, wherein the state of each control signal is a function of the state of the M inputs of said decoder means, a selected state of the M inputs of said decoder means causes each control signal from said decoder means to assume said off state, and wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and said decoder means comprises a one of N decoder circuit.

Claim 6

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a decoder/driver means associated with each of said user re-programmable interconnect elements, each of said decoder/driver means having a first input and a second input, for decoding input signals and an output connected to a single associated user re-programmable interconnect element, for driving its associated user re-programmable interconnect element in response to signals at its first and second inputs; M 1 first active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 1 is an integer, the output of each of said first active storage elements connected to the first inputs of a different subset of said decoder/driver means; M 2 second active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 2 is an integer, the output of each of said second active storage elements connected to the second inputs of a different subset of said decoder/driver means such that the first and second inputs of each of said decoder/driver means are connected to the outputs of one each of said first and second active storage elements; and wherein each of said decoder/driver means will switch its associated user re-programmable interconnect element to its on state in response to said selected state outputs appearing at both its first and second inputs, and wherein M 1 +M 2 <N.

Claim 7

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a decoder/driver means associated with each of said user re-programmable interconnect elements, each of said decoder/driver means having a first input and a second input, for decoding input signals and an output connected to a single associated user re-programmable interconnect element, for driving its associated user re-programmable interconnect element in response to signals at its first and second inputs; M 1 first active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 1 is an integer, the output of each of said first active storage elements connected to the first inputs of a different subset of said decoder/driver means; M 2 second active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 2 is an integer, the output of each of said second active storage elements connected to the second inputs of a different subset of said decoder/driver means such that the first and second inputs of each of said decoder/driver means are connected to the outputs of one each of said first and second active storage elements; and wherein each of said decoder/driver means will switch its associated user re-programmable interconnect element to its on state in response to said selected state outputs appearing at both its first and second inputs, and wherein M 1 +M 2 <N.

Claim 8

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a decoder/driver means associated with each of said user re-programmable interconnect elements, each of said decoder/driver means having a first input and a second input, for decoding input signals and an output connected to its associated user re-programmable interconnect element, for driving its associated user re-programmable interconnect element in response to signals at its first and second inputs; M 1 first active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 1 is an integer, the output of each of said first active storage elements connected to the first inputs of a different subset of said decoder/driver means; M 2 second active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 2 is an integer, the output of each of said second active storage elements connected to the second inputs of a different subset of said decoder/driver means such that the first and second inputs of each of said decoder/driver means are connected to the outputs of one each of said first and second active storage elements; wherein each of said decoder/driver means will switch its associated user re-programmable interconnect element to its on state in response to said selected state outputs appearing at both its first and second inputs, and wherein M 1 +M 2 <N and wherein said active storage elements comprise SRAM cells, said user-reprogrammable interconnect elements comprise MOS transistors, and said decoder/driver means comprise ANDing circuits.

Claim 9

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a decoder/driver means associated with each of said user re-programmable interconnect elements, each of said decoder/driver means having a first input and a second input, for decoding input signals and an output connected to its associated user re-programmable interconnect element, for driving its associated user re-programmable interconnect element in response to signals at its first and second inputs; M 1 first active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 1 is an integer, the output of each of said first active storage elements connected to the first inputs of a different subset of said decoder/driver means; M 2 second active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 2 is an integer, the output of each of said second active storage elements connected to the second inputs of a different subset of said decoder/driver means such that the first and second inputs of each of said decoder/driver means are connected to the outputs of one each of said first and second active storage elements; wherein each of said decoder/driver means will switch its associated user re-programmable interconnect element to its on state in response to said selected state outputs appearing at both its first and second inputs, and wherein M 1 +M 2 <N and wherein said active storage elements comprise SRAM cells, said user-reprogrammable interconnect elements comprise MOS transistors, and said decoder/driver means comprise ANDing circuits.

Claim 10

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements switchable between an on state and an off state in response to the state of a control signal; M 1 first active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 1 is an integer; first decoder means having M 1 inputs connected to outputs of said first active storage elements and having a plurality of outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements in a first subgroup thereof, wherein the state of each control signal is a function of the state of the M 1 inputs of said first decoder means; M 2 second active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 2 is an integer; and second decoder means having M 2 inputs connected to outputs of said active storage elements and having a plurality of outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements in a second subgroup thereof, wherein the state of each control signal is a function of the state of the M 2 inputs of said second decoder means; and wherein M 1 +M 2 <N.

Claim 11

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements switchable between an on state and an off state in response to the state of a control signal; M 1 first active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 1 is an integer; first decoder means having M 1 inputs connected to outputs of said first active storage elements and having a plurality of outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements in a first subgroup thereof, wherein the state of each control signal is a function of the state of the M 1 inputs of said first decoder means; M 2 second active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 2 is an integer; and second decoder means having M 2 inputs connected to outputs of said active storage elements and having a plurality of outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements in a second subgroup thereof, wherein the state of each control signal is a function of the state of the M 2 inputs of said second decoder means; and wherein M 1 +M 2 <N.

Claim 12

The user re-programmable interconnect architecture of claim 6 wherein: a selected state of the M 1 inputs of said first decoder means causes each control signal from said first decoder means to assume said off state; and a selected state of the M 2 inputs of said second decoder means causes each control signal from said second decoder means to assume said off state.

Claim 13

The user re-programmable interconnect architecture of claim 7 wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and said first and second decoder means comprise a one of N decoder circuit.

Claim 14

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements having a first control input and a second control input, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of an internally-generated control signal; M 1 first active storage elements, each having a first unselected state and a second selected state and an output, where M 1 is an integer, the output of each first active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to a first control input of each of a first group of said user re-programmable interconnect elements; M 2 second active storage elements, each having a first unselected state and a second selected state and an output, where M 2 is an integer, the output of each second active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to a second control input of a second group of said user re-programmable interconnect elements such that each of said user re-programmable interconnect elements is connected to an output from one of said first and one of said second active storage elements; control-signal generating means, in each of said user re-programmable interconnect elements, for generating said control signal to place it in its on state in response to the presence of on output signals from the first and second active storage elements to which it is connected; and wherein M 1 +M 2 <N.

Claim 15

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements having a first control input and a second control input, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of an internally-generated control signal; M 1 first active storage elements, each having a first unselected state and a second selected state and an output, where M 1 is an integer, the output of each first active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to a first control input of each of a first group of said user re-programmable interconnect elements; M 2 second active storage elements, each having a first unselected state and a second selected state and an output, where M 2 is an integer, the output of each second active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to a second control input of a second group of said user re-programmable interconnect elements such that each of said user re-programmable interconnect elements is connected to an output from one of said first and one of said second active storage elements; control-signal generating means, in each of said user re-programmable interconnect elements, for generating said control signal to place it in its on state in response to the presence of on output signals from the first and second active storage elements to which it is connected; and wherein M 1 +M 2 <N.

Claim 16

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements having a first control input and a second control input, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of an internally-generated control signal; M 1 first active storage elements, each having a first unselected state and a second selected state and an output, where M 1 is an integer, the output of each first active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to a first control input of each of a first group of said user re-programmable interconnect elements; M 2 second active storage elements, each having a first unselected state and a second selected state and an output, where M 2 is an integer, the output of each second active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to a second control input of a second group of said user re-programmable interconnect elements such that each of said user re-programmable interconnect elements is connected to an output from one of said first and one of said second active storage elements; control-signal generating means, in each of said user re-programmable interconnect elements, for generating said control signal to place it in its on state in response to the presence of on output signals from the first and second active storage elements to which it is connected; wherein M 1 +M 2 <N and wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and each of said control signal generating means comprises an ANDing circuit.

Claim 17

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements having a first control input and a second control input, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of an internally-generated control signal; M 1 first active storage elements, each having a first unselected state and a second selected state and an output, where M 1 is an integer, the output of each first active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to a first control input of each of a first group of said user re-programmable interconnect elements; M 2 second active storage elements, each having a first unselected state and a second selected state and an output, where M 2 is an integer, the output of each second active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to a second control input of a second group of said user re-programmable interconnect elements such that each of said user re-programmable interconnect elements is connected to an output from one of said first and one of said second active storage elements; control-signal generating means, in each of said user re-programmable interconnect elements, for generating said control signal to place it in its on state in response to the presence of on output signals from the first and second active storage elements to which it is connected; wherein M 1 +M 2 <N and wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and each of said control signal generating means comprises an ANDing circuit.

Claim 18

A user re-programmable interconnect architecture disposed on a microcircuit substrate comprising: an input/output pad; a first input/output pad conductor extending in a first direction from said input/output pad; a second input/output pad conductor extending in a second direction from said input/output pad, said second direction substantially different from said first direction; a plurality of first interconnect conductors insulated from and intersecting said first input/output pad conductor; a plurality of second interconnect conductors insulated from and intersecting said second input/output pad conductor, said second interconnect conductors insulated from and forming intersections with said first interconnect conductors; a plurality of first user re-programmable interconnect elements, one of said first user re-programmable interconnect elements connected between each of said first interconnect conductors and said first input/output pad conductor, each of said first user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a first plurality of active storage elements, each one of said first plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of first user re-programmable interconnect elements in response to its state; a plurality of second user re-programmable interconnect elements, one of said second user re-programmable interconnect elements connected between each of said second interconnect conductors and said second input/output pad conductor, each of said second user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a second plurality of active storage elements, each one of said second plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of second user re-programmable interconnect elements in response to its state; N third user re-programmable interconnect elements, where N is an integer, one of said third user re-programmable interconnect elements connected at selected ones of said intersections between said first and second interconnect conductors, each of said third user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M 1 third active storage elements each having an output and having a first unselected state and a second selected state, where M 1 is an integer, the output of each third active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one first control input of each of a first group of said third user re-programmable interconnect elements; M 2 fourth active storage elements, each having an output and a first unselected state and a second selected state, where M 2 is an integer, the output of each fourth active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one second control input of a second group of said third user re-programmable interconnect elements, said first group and said second group chosen such that each of said user re-programmable interconnect elements is connected to an output from one of said third and one of said fourth active storage elements; control-signal generating means, in each of said third user re-programmable interconnect elements, for generating said control signal to place it in its on state in response to the presence of an output signals from the third and fourth active storage elements to which it is connected; and wherein M 1 +M 2 <N.

Claim 19

A user re-programmable interconnect architecture disposed on a microcircuit substrate comprising: an input/output pad; a first input/output pad conductor extending in a first direction from said input/output pad; a second input/output pad conductor extending in a second direction from said input/output pad, said second direction substantially different from said first direction; a plurality of first interconnect conductors insulated from and intersecting said first input/output pad conductor; a plurality of second interconnect conductors insulated from and intersecting said second input/output pad conductor, said second interconnect conductors insulated from and forming intersections with said first interconnect conductors; a plurality of first user re-programmable interconnect elements, one of said first user re-programmable interconnect elements connected between each of said first interconnect conductors and said first input/output pad conductor, each of said first user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a first plurality of active storage elements, each one of said first plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of first user re-programmable interconnect elements in response to its state; a plurality of second user re-programmable interconnect elements, one of said second user re-programmable interconnect elements connected between each of said second interconnect conductors and said second input/output pad conductor, each of said second user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a second plurality of active storage elements, each one of said second plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of second user re-programmable interconnect elements in response to its state; N third user re-programmable interconnect elements, where N is an integer, one of said third user re-programmable interconnect elements connected at selected ones of said intersections between said first and second interconnect conductors, each of said third user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M 1 third active storage elements each having an output and having a first unselected state and a second selected state, where M 1 is an integer, the output of each third active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one first control input of each of a first group of said third user re-programmable interconnect elements; M 2 fourth active storage elements, each having an output and a first unselected state and a second selected state, where M 2 is an integer, the output of each fourth active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one second control input of a second group of said third user re-programmable interconnect elements, said first group and said second group chosen such that each of said user re-programmable interconnect elements is connected to an output from one of said third and one of said fourth active storage elements; control-signal generating means, in each of said third user re-programmable interconnect elements, for generating said control signal to place it in its on state in response to the presence of an output signals from the third and fourth active storage elements to which it is connected; and wherein M 1 +M 2 <N.

Claim 20

The user re-programmable interconnect architecture of claim 11 wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and each of said control-signal generating means comprises an ANDing circuit.

Claim 21

A user re-programmable interconnect architecture disposed on a microcircuit substrate comprising: a plurality of I/O structures arranged in a matrix of rows and columns, each of said I/O structures comprising an I/O pad, a first input/output pad conductor extending in a first direction from said input output pad and a second input/output pad conductor extending in a second direction from said input/output pad, said second direction substantially different from said first direction; a row group of first interconnect conductors in each row of said array, each of said first interconnect conductors in each row group insulated from and intersecting said first input/output pad conductors of each of said I/O structures in their row; a column group of second interconnect conductors in each column of said array, each of said second interconnect conductors in each column group insulated from and intersecting said second input/output pad conductors of each of said I/O structures in their column, said second interconnect conductors insulated from and forming intersections with said first interconnect conductors in each row group thereof; a plurality of first user re-programmable interconnect elements, one of said first user re-programmable interconnect elements connected between each of said first interconnect conductors and said first input/output pad conductors at intersections thereof, each of said first user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a first plurality of active storage elements, each one of said first plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of first user re-programmable interconnect elements in response to its state; a plurality of second user re-programmable interconnect elements, one of said second user re-programmable interconnect elements connected between each of said second interconnect conductors and said second input/output pad conductors at intersections thereof, each of said second user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a second plurality of active storage elements, each one of said second plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of second user re-programmable interconnect elements in response to its state; N third user re-programmable interconnect elements associated with each intersecting row group and column group of interconnect conductors in each I/O structure, where N is an integer, one of said third user re-programmable interconnect elements connected at selected ones of said intersections between said first and second interconnect conductors, each of said third user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M 1 third active storage elements associated with each intersecting row group and column group of interconnect conductors in each I/O structure, each having an output and having a first unselected state and a second selected state, where M 1 is an integer, the output of each third active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one first control input of each of a first group of said third user re-programmable interconnect elements in its I/O structure; M 2 fourth active storage elements associated with each intersecting row group and column group of interconnect conductors in each I/O structure, each having an output and a first unselected state and a second selected state, where M 2 is an integer, the output of each fourth active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one second control input of a second group of said third user re-programmable interconnect elements in its I/O structure, said first group and said second group chosen such that each of said user re-programmable interconnect elements is connected to an output from one of said third and one of said fourth active storage elements; control-signal generating means, in each of said third user re-programmable interconnect elements, for generating said control signal to place it in its on state in response to the presence of on output signals from the third and fourth active storage elements to which it is connected; and wherein M 1 +M 2 <N.

Claim 22

A user re-programmable interconnect architecture disposed on a microcircuit substrate comprising: a plurality of I/O structures arranged in a matrix of rows and columns, each of said I/O structures comprising an I/O pad, a first input/output pad conductor extending in a first direction from said input output pad and a second input/output pad conductor extending in a second direction from said input/output pad, said second direction substantially different from said first direction; a row group of first interconnect conductors in each row of said array, each of said first interconnect conductors in each row group insulated from and intersecting said first input/output pad conductors of each of said I/O structures in their row; a column group of second interconnect conductors in each column of said array, each of said second interconnect conductors in each column group insulated from and intersecting said second input/output pad conductors of each of said I/O structures in their column, said second interconnect conductors insulated from and forming intersections with said first interconnect conductors in each row group thereof; a plurality of first user re-programmable interconnect elements, one of said first user re-programmable interconnect elements connected between each of said first interconnect conductors and said first input/output pad conductors at intersections thereof, each of said first user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a first plurality of active storage elements, each one of said first plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of first user re-programmable interconnect elements in response to its state; a plurality of second user re-programmable interconnect elements, one of said second user re-programmable interconnect elements connected between each of said second interconnect conductors and said second input/output pad conductors at intersections thereof, each of said second user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a second plurality of active storage elements, each one of said second plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of second user re-programmable interconnect elements in response to its state; N third user re-programmable interconnect elements associated with each intersecting row group and column group of interconnect conductors in each I/O structure, where N is an integer, one of said third user re-programmable interconnect elements connected at selected ones of said intersections between said first and second interconnect conductors, each of said third user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M 1 third active storage elements associated with each intersecting row group and column group of interconnect conductors in each I/O structure, each having an output and having a first unselected state and a second selected state, where M 1 is an integer, the output of each third active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one first control input of each of a first group of said third user re-programmable interconnect elements in its I/O structure; M 2 fourth active storage elements associated with each intersecting row group and column group of interconnect conductors in each I/O structure, each having an output and a first unselected state and a second selected state, where M 2 is an integer, the output of each fourth active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one second control input of a second group of said third user re-programmable interconnect elements in its I/O structure, said first group and said second group chosen such that each of said user re-programmable interconnect elements is connected to an output from one of said third and one of said fourth active storage elements; control-signal generating means, in each of said third user re-programmable interconnect elements, for generating said control signal to place it in its on state in response to the presence of on output signals from the third and fourth active storage elements to which it is connected; and wherein M 1 +M 2 <N.

Claim 23

The user re-programmable interconnect architecture of claim 13 wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and each of said control-signal generating means comprises an ANDing circuit.