Critical dimension control with a planarized underlayer

Claim 1

The method of planarizing an integrated circuit while controlling the critical dimension of polysilicon layer during etching in the formation of a polysilicon gate electrode comprising: providing semiconductor device structures including bare active areas surrounded by field oxide isolation on a semiconductor substrate wherein the surface of said substrate has an uneven topography due to the uneven interface between said active areas and said isolation; depositing said polysilicon layer over said active areas and said field oxidation of said substrate wherein the width of said polysilicon layer is said critical dimension; covering said polysilicon layer with a spin-on-glass layer wherein said spin-on-glass planarizes the surface of said substrate; covering said spin-on-glass layer with a uniform thickness layer of photoresist; exposing, developing and patterning said photoresist layer to form the desired photoresist mask for said polysilicon layer; anisotropically etching said exposed spin-on-glass and polysilicon layers wherein said etching said polysilicon causes a polymer to form on the sidewalls of said polysilicon; removing said photoresist mask; and simultaneously removing and spin-on-glass layer and said polymer to complete said polysilicon gate electrode having said critical dimension in said integrated circuit.

Claim 2

The method of planarizing an integrated circuit while controlling the critical dimension of polysilicon layer during etching in the formation of a polysilicon gate electrode comprising: providing semiconductor device structures including bare active areas surrounded by field oxide isolation on a semiconductor substrate wherein the surface of said substrate has an uneven topography due to the uneven interface between said active areas and said isolation; depositing said polysilicon layer over said active areas and said field oxidation of said substrate wherein the width of said polysilicon layer is said critical dimension; covering said polysilicon layer with a spin-on-glass layer wherein said spin-on-glass planarizes the surface of said substrate; covering said spin-on-glass layer with a uniform thickness layer of photoresist; exposing, developing and patterning said photoresist layer to form the desired photoresist mask for said polysilicon layer; anisotropically etching said exposed spin-on-glass and polysilicon layers wherein said etching said polysilicon causes a polymer to form on the sidewalls of said polysilicon; removing said photoresist mask; and simultaneously removing and spin-on-glass layer and said polymer to complete said polysilicon gate electrode having said critical dimension in said integrated circuit.

Claim 10

The method of etching a polysilicon layer while controlling the critical dimension of the polysilicon layer to be uniform comprising: providing a substrate wherein the surface of said substrate has an uneven topography; depositing said polysilicon layer over said uneven surface of said substrate wherein the width of said polysilicon layer is said critical dimension; covering said polysilicon layer with a spin-on-glass layer wherein said spin-on-glass planarizes the surface of said substrate; covering said spin-on-glass layer with a uniform thickness layer of photoresist; exposing, developing and patterning said photoresist layer to form the desired photoresist mask for said polysilicon layer; anisotropically etching said exposed spin-on-glass and polysilicon layers down to said substrate wherein said etching said polysilicon causes a polymer to form on the sidewalls of said polysilicon; removing said photoresist mask; and simultaneously removing said spin-on-glass layer and said polymer to complete said polysilicon layer having said critical dimension.

Claim 11

The method of etching a polysilicon layer while controlling the critical dimension of the polysilicon layer to be uniform comprising: providing a substrate wherein the surface of said substrate has an uneven topography; depositing said polysilicon layer over said uneven surface of said substrate wherein the width of said polysilicon layer is said critical dimension; covering said polysilicon layer with a spin-on-glass layer wherein said spin-on-glass planarizes the surface of said substrate; covering said spin-on-glass layer with a uniform thickness layer of photoresist; exposing, developing and patterning said photoresist layer to form the desired photoresist mask for said polysilicon layer; anisotropically etching said exposed spin-on-glass and polysilicon layers down to said substrate wherein said etching said polysilicon causes a polymer to form on the sidewalls of said polysilicon; removing said photoresist mask; and simultaneously removing said spin-on-glass layer and said polymer to complete said polysilicon layer having said critical dimension.