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Thin film transistor and its production method

Assignee: Vista Peak Ventures LLC
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Filing: 1992-09-30
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Granted: 1994-07-12
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Expires: 2012-09-30
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Abstract

Abstract A thin film transistor having a larger ON-OFF current ratio is provided, in which a first insulating film having a first and second contact holes is formed on a substrate so as to cover a source and drain regions formed therein and a semiconductor film is formed on the first insulating film so as to be connected through the holes respectively to the source and drain regions. A second insulating film is formed on the semiconductor film and a gate electrode is formed thereon so as not be overlapped with the holes. In the offset region between each end of the gate electrode and the corresponding one of the holes, the insulation between the semiconductor film and the source and drain regions is provided by the first insulating film. This semiconductor film is weakly inverted by a drain voltage in the offset region, resulting in obtaining a leak current suppression action. The semiconductor film is preferable to be a polysilicon film.

Inventors

  • 👤 Kenji Sera

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 07:37
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 181 words
A thin film transistor comprising: a source region and a drain region formed of an electroconductive film on an substrate at aninterval; a first insulating film formed on said substrate so as to cover said source region and said drain region and having a first contact hole on said source region and a second contact hole on said drain region; a semiconductor film formed on said first insulating film so as to be connected through said first contact hole and said second contact hole formed in said first insulating film respectively to said source region and said drain region; a second insulating film formed on said semiconductor film; and a gate electrode formed of an electroconductive film on said second insulating film so as not to be overlapped with said first contact hole and said second contact hole; wherein in the space between each end of said gate electrode and the corresponding one of said first contact hole and said second contact hole, there exists said first insulating film between said semiconductor film and said source region and said drain region.
Claim 2
Dependent Claim 181 words
A thin film transistor comprising: a source region and a drain region formed of an electroconductive film on an substrate at aninterval; a first insulating film formed on said substrate so as to cover said source region and said drain region and having a first contact hole on said source region and a second contact hole on said drain region; a semiconductor film formed on said first insulating film so as to be connected through said first contact hole and said second contact hole formed in said first insulating film respectively to said source region and said drain region; a second insulating film formed on said semiconductor film; and a gate electrode formed of an electroconductive film on said second insulating film so as not to be overlapped with said first contact hole and said second contact hole; wherein in the space between each end of said gate electrode and the corresponding one of said first contact hole and said second contact hole, there exists said first insulating film between said semiconductor film and said source region and said drain region.
Claim 3
Dependent Claim 17 words
The thin film transistor as claimed in claim 1, wherein said semiconductor film is a polysilicon film.
Claim 4
Dependent Claim 24 words
The thin film transistor as claimed in claim 1, wherein said gate electrode is partially overlapped with said source region and said drain region.
Claim 5
Dependent Claim 24 words
The thin film transistor as claimed in claim 2, wherein said gate electrode is partially overlapped with said source region and said drain region.

References Cited (Backward Citations)

US4630089A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-07-11 1998-01-10 1998-07-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-07-11 2002-01-10 2002-07-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-07-11 2006-01-10 2006-07-12 $7700.00 Window Closed / Lapsed

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