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Antifuse with nonstoichiometric tin layer and method of manufacture thereof

Assignee: Crosspoint Solutions Inc
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Filing: 1992-04-10
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Granted: 1994-07-12
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Expires: 2012-04-10
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Abstract

Abstract An antifuse in an integrated circuit which has first and second conducting lines, a semiconductor layer of amorphous silicon between the first and second conducting lines, and a barrier metal layer of TiN between the semiconductor layer and the first conducting layer is disclosed. The TiN layer is nonstoichiometric composition to enhance the probability of said antifuse having a desired resistance when said antifuse is programmed. More specifically, the TiN layer has a composition of Ti 1 .0 N 0 .5-0.8.

Inventors

  • 👤 Pankaj Dixit

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 02:55
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; H10W20/49; H10W20/491

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 62 words
In an integrated circuit an antifuse comprising first and second conducting lines; a semiconductor layer between said first and second conducting lines; and a barrier metal layer of TiN between said semiconductor layer and said first conducting layer, said TiN layer being of nonstoichiometric composition; whereby the probability of said antifuse having a desired resistance when said antifuse is programmed is enhanced.
Claim 2
Dependent Claim 62 words
In an integrated circuit an antifuse comprising first and second conducting lines; a semiconductor layer between said first and second conducting lines; and a barrier metal layer of TiN between said semiconductor layer and said first conducting layer, said TiN layer being of nonstoichiometric composition; whereby the probability of said antifuse having a desired resistance when said antifuse is programmed is enhanced.
Claim 3
Dependent Claim 19 words
The antifuse of claim 1 wherein said TiN layer has a composition of Ti 1 .0 N 0 .5-0.8.
Claim 4
Dependent Claim 16 words
The antifuse of claim 1 wherein said second conducting layer lies over said first conducting layer.
Claim 5
Dependent Claim 26 words
The antifuse of claim 1 wherein said second conducting layer has a positive voltage with respect to said first programming layer when said antifuse is programmed.
Claim 6
Dependent Claim 16 words
The antifuse of claim 4 wherein said second conducting layer lies over said first conducting layer.
Claim 7
Dependent Claim 21 words
The antifuse of claim 1 further comprising a second barrier metal layer between said semiconductor layer and said second conducting layer.
Claim 8
Dependent Claim 12 words
The antifuse of claim 1 wherein said semiconductor layer comprises amorphous silicon.
Claim 9
Dependent Claim 14 words
The antifuse of claim 1 wherein said first and second conducting layers comprise metal.
Claim 10
Dependent Claim 98 words
In an integrated circuit having a semiconductor substrate and an insulating layer formed thereover, an antifuse comprising a first metal interconnection layer on said insulating layer; a first barrier metal layer on said first metal conducting layer; a semiconductor layer on said first barrier metal layer; a second barrier metal layer on said semiconductor layer; and a second metal interconnection layer on said second barrier metal layer; at least one of said barrier metal layers formed by nonstoichiometric composition of TiN whereby the probability of said antifuse having a desired resistance when said antifuse is programmed is enhanced.
Claim 11
Dependent Claim 98 words
In an integrated circuit having a semiconductor substrate and an insulating layer formed thereover, an antifuse comprising a first metal interconnection layer on said insulating layer; a first barrier metal layer on said first metal conducting layer; a semiconductor layer on said first barrier metal layer; a second barrier metal layer on said semiconductor layer; and a second metal interconnection layer on said second barrier metal layer; at least one of said barrier metal layers formed by nonstoichiometric composition of TiN whereby the probability of said antifuse having a desired resistance when said antifuse is programmed is enhanced.
Claim 12
Dependent Claim 19 words
The antifuse of claim 9 wherein said TiN layer has a composition of Ti 1 .0 N 0 .5-0.8.
Claim 13
Dependent Claim 52 words
The antifuse of claim 10 wherein one of said metal interconnection layers has a positive voltage with respect to the second of said metal interconnection layers during the programming of said antifuse, said barrier metal layer of nonstoichiometric TiN located opposite said one metal interconnection line with respect to said semiconductor layer.
Claim 14
Dependent Claim 12 words
The antifuse of claim 11 wherein said semiconductor layer comprises amorphous silicon.
Claim 15
Dependent Claim 15 words
The antifuse of claim 12 wherein said first and second metal interconnection lines comprise aluminum.

References Cited (Backward Citations)

US3571673A Cited
US3675090A Cited
US4458297A Cited
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US4796074A Cited
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US5191550A Cited
US5070384A Cited
WO1992013359A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-07-11 1998-01-10 1998-07-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-07-11 2002-01-10 2002-07-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-07-11 2006-01-10 2006-07-12 $7700.00 Window Closed / Lapsed

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