Method and system for logic change in an automatic logic synthesis system

Claim 3

The method for logic change in an automatic logic synthesis system as defined in claim 1, further comprising: providing third identifiers each of which indicates whether or not a lower-rank description corresponding to the description unit data of the higher-rank description exists; setting the third identifier of the higher-rank description unit from which the lower-rank description has been synthesized, at the origination; and originating and registering lower-rank description unit data anew as to the higher-rank description unit whose third identifier is not set, in the automatic logic synthesis.

Claim 6

The system for logic change in an automatic logic synthesis system as defined in claim 3, wherein: said storage means includes an area for storing third identifiers each of which indicates whether or not a lower-rank description of the corresponding higher-rank description unit data exists; and said data processing means originates and registers lower-rank description unit data anew as to the higher rank description unit whose third identifier is not set, and it sets the third identifier of the higher-rank description unit, in the automatic logic synthesis.

Claim 7

The system for logic change in an automatic logic synthesis system as defined in claim 4, further comprising: a first automatic logic synthesis terminal including a first storage and a first data processor, a second automatic logic synthesis terminal including a second storage and a second data processor, and a communication line which connects said first automatic logic synthesis terminal and said second automatic logic synthesis terminal; said first storage including an area for storing the higher-rank descriptions, the first identifiers each of which indicates the presence of the description change of the corresponding higher-rank description unit data, and the third identifiers each of which indicates whether or not the lower-rank description of the corresponding higher-rank description unit data exists; said second storage including an area for storing the lower-rank descriptions, and the second identifiers each of which indicates the presence of the description change of the corresponding lower rank description unit data; said first data processor including: access means for accessing to the lower-rank description data stored in said second storage, through said communication line, the higher-rank description edit means for setting the first identifier of the changed higher-rank description unit data at the change of the higher rank description, the lower-rank description edit means for setting the second identifier of the changed description unit stored in said second storage, at the change of the lower-rank description directly made without any synthesis process from the higher-rank description, and the automatic logic synthesis means for originating the lower-rank description unit data anew as regards the higher-rank description unit whose third identifier is not set, so as to register the synthesized data in said second storage, and for setting the third identifier of the higher-rank description unit, and for originating the new lower-rank description unit data as regards the higher-rank description unit whose third identifier is set and whose first identifier is set, whereupon on condition that the second identifier of the current lower-rank description unit data corresponding to the new lower-rank description unit data is not set, said means registers the new lower-rank description unit data in said second storage as lower rank description unit data, and on condition that the second identifier of the current lower-rank description unit data is set, said means merges the new lower-rank description unit data and the current lower-rank description unit data and registers a merged result in said second storage as lower rank description unit data; said storage means being constructed of said first storage and said second storage, while said data processing means is constructed of said first data processor.

Claim 8

The system for logic change in an automatic logic synthesis system as defined in claim 4, further comprising: a first automatic logic synthesis terminal including a first storage and a first data processor, at least one second automatic logic synthesis terminal including a second storage and a second data processor, and at least one communication line which connects said first automatic logic synthesis terminal and said second at least one automatic logic synthesis terminal; said first storage including an area for storing the higher-rank descriptions, the first identifiers each of which indicates the presence of the description change of the corresponding higher-rank description unit data, and the third identifiers each of which indicates whether or not the lower-rank description of the corresponding higher-rank description unit data exists; said second storage including an area for storing the lower-rank descriptions, and the second identifiers each of which indicates the presence of the description change of the corresponding lower-rank description unit data; said first data processor including access means for accessing to the lower-rank description data stored in said second storage, through said communication line, the higher-rank description edit means for setting the first identifier of the changed description unit data at the change of the higher-rank description, the lower-rank description edit means for setting the second identifier of the changed description unit stored in said second storage, at the change of the lower-rank description directly made without any synthesis process from the higher-rank description, and means for transmitting the higher-rank description unit whose third identifier is not set and the higher-rank description unit whose first identifier is set, to said second data processor at the automatic logic synthesis; said second data processor including the automatic logic synthesis means for originating and registering the lower-rank description unit data anew as to the higher-rank description unit which is transmitted from said first data processor and whose third identifier is not set, and for setting the third identifier of the higher-rank description unit stored in said first storage, in the automatic logic synthesis, and for originating the new lower-rank description unit data as regards the higher-rank description unit whose third identifier is set and whose first identifier is set, whereupon on condition that the second identifier of the current lower-rank description unit data corresponding to the new lower-rank description unit data is not set, said means registers the new lower-rank description unit data as lower-rank description unit data, and on condition that the second identifier of the current lower-rank description unit data is set, said means merges the new lower-rank description unit data and the current lower-rank description unit data and registers a merged result as lower-rank description unit data; said storage means being constructed of said first storage and said second storage, while said data processing means is constructed of said first data processor and said second data processor.