Memory IC testing apparatus with redundancy circuit

Claim 2

A testing apparatus for testing a memory IC having a redundancy circuit, comprising: first memory means having a memory area for row addresses of a target memory, for storing row addresses of defective bits of the target memory; counter means for counting a number of defective-bit containing rows of the target memory; second memory means for storing a number of rows of spare memory cells provided in the redundance circuit; and first comparator means for comparing a count value of said counter means with a number of rows stored in said second memory means, wherein when the count value of said counter means exceeds the number of rows of spare memory cells stored in said second memory means, a test is terminated because the target memory is judged as unrepairable, and when the count value does not exceed the number of rows of spare memory cells stored in said second memory means, memory cells in a defective-bit containing row in the target memory are replaced with memory cells in an associated row in the redundancy circuit based on the row addresses stored in said first memory means.

Claim 3

A testing apparatus according to claim 1, further comprising: pattern generator means for generating and supplying address signal and data for test to the target memory, said pattern generator means being disabled when said first comparator means outputs a signal representing an unrepairable state; second comparator means for comparing data read out from the target memory with the data from said pattern generator means; and control means for receiving an output of said second comparator means and the address signal from said pattern generator means, and performing control to write row addresses of defective bits in said first memory means when the data read out from the target memory differs from said data from said pattern generator means.

Claim 4

A testing apparatus according to claim 1, further comprising third memory means having a memory area for row addresses of the target memory, for storing presence of defective bits in the target memory, said counter means being counted up when defect information is written in said third memory means.

Claim 5

A testing apparatus for testing a memory IC having a redundancy circuit, comprising: first memory means having a memory area for row addresses of a target memory, for storing row addresses of defective bits of the target memory; second memory means having a memory area for column addresses of the target memory, for storing column addresses of defective bits of the target memory; first counter means for counting a number of defective-bit containing rows of the target memory; second counter means for counting a number of defective-bit containing columns of the target memory; third memory means for storing a number of rows of spare memory cells provided in the redundancy circuit; fourth memory means for storing a number of columns of spare memory cells provided in the redundance circuit; first comparator means for comparing a count value of said first counter means with a number of rows stored in said third memory means; second comparator means for comparing a count value of said second counter means with a number of columns stored in said fourth memory means; and logical product means for acquiring a logical product of comparison outputs of said first and second comparator means and outputting a repair enable signal representing a repairable state, wherein when the repair enable signal is output, memory cells in at least one of a defective-bit containing row and a defective-bit containing column in the target memory are replaced with memory cells in at least one of an associated row and an associated column in the redundance circuit based on the row addresses of defective bits stored in said first memory means and the column addresses of defective bits stored in said second memory means.

Claim 6

A testing apparatus for testing a memory IC having a redundancy circuit, comprising: first memory means having a memory area for row addresses of a target memory, for storing row addresses of defective bits of the target memory; second memory means having a memory area for column addresses of the target memory, for storing column addresses of defective bits of the target memory; first counter means for counting a number of defective-bit containing rows of the target memory; second counter means for counting a number of defective-bit containing columns of the target memory; third memory means for storing a number of rows of spare memory cells provided in the redundancy circuit; fourth memory means for storing a number of columns of spare memory cells provided in the redundance circuit; first comparator means for comparing a count value of said first counter means with a number of rows stored in said third memory means; second comparator means for comparing a count value of said second counter means with a number of columns stored in said fourth memory means; and logical product means for acquiring a logical product of comparison outputs of said first and second comparator means and outputting a repair enable signal representing a repairable state, wherein when the repair enable signal is output, memory cells in at least one of a defective-bit containing row and a defective-bit containing column in the target memory are replaced with memory cells in at least one of an associated row and an associated column in the redundance circuit based on the row addresses of defective bits stored in said first memory means and the column addresses of defective bits stored in said second memory means.

Claim 7

A testing apparatus according to claim 4, further comprising: pattern generator means for generating and supplying an address signal and data for test to the target memory; third comparator means for comparing data read out from the target memory with the data from said pattern generator means; and control means for receiving an output of said third comparator means and the address signal from said pattern generator means, and performing control to write row addresses of defective bits in said first memory means and write column addresses of defective bits in said second memory means when the data read out from the target memory differs from the data from said pattern generator means.

Claim 8

A testing apparatus according to claim 4, further comprising: fifth memory means having a memory area for row addresses of the target memory, for storing presence of defective-bit containing rows in the target memory; and sixth memory means having a memory area for column addresses of the target memory, for storing presence of defective-bit containing columns in the target memory, said first counter means being counted up when defect information is written in said fifth memory means, and said second counter means being counted up when defect information is written in said sixth memory means.

Claim 9

A testing apparatus for a memory IC with a redundancy circuit, comprising: first memory means for address failure, having at least a same memory area as a target memory, for storing defect information; first counter means for counting a number of defective-bit rows based on said defect information stored in said first memory means; second counter means for counting a number of defective-bit columns based on the defect information stored in said first memory means; second memory means for storing row addresses of defective bits of the target memory, with a number of defective bits present in the same row being taken as an address; and third memory means for storing column addresses of defective bits of the target memory, with a number of defective bits present in the same column being taken as an address, wherein memory cells in at least one of a defective-bit containing row and a defective-bit containing column in the target memory are replaced with memory cells in at least one of an associated row and an associated column in the redundancy circuit based on the row addresses of defective bits stored in said second memory means and the column addresses of defective bits stored in said third memory means.

Claim 10

A testing apparatus for a memory IC with a redundancy circuit, comprising: first memory means for address failure, having at least a same memory area as a target memory, for storing defect information; first counter means for counting a number of defective-bit rows based on said defect information stored in said first memory means; second counter means for counting a number of defective-bit columns based on the defect information stored in said first memory means; second memory means for storing row addresses of defective bits of the target memory, with a number of defective bits present in the same row being taken as an address; and third memory means for storing column addresses of defective bits of the target memory, with a number of defective bits present in the same column being taken as an address, wherein memory cells in at least one of a defective-bit containing row and a defective-bit containing column in the target memory are replaced with memory cells in at least one of an associated row and an associated column in the redundancy circuit based on the row addresses of defective bits stored in said second memory means and the column addresses of defective bits stored in said third memory means.

Claim 11

A testing apparatus according to claim 7, further comprising: pattern generator means for generating and supplying address signal and data for test to the target memory; comparator means for comparing data read out from the target memory with the data from said pattern generator means; and control means for receiving an output of said comparator means and the address signal from said pattern generator means, and performing control to write row addresses of defective bits in said second memory means and write column addresses of defective bits in said third memory means when the data read out from the target memory differs from the data from said pattern generator means.

Claim 12

A testing apparatus according to claim 8, further comprising: first selector means for writing fail row addresses as data into said second memory means, with a number of defective bits being taken as an address, under control of said control means; and second selector means for writing fail column addresses as data into said third memory means, with a number of defective bits being taken as an address, under control of said control means.

Claim 13

A testing apparatus for testing a memory IC having a redundance circuit, comprising: a first testing section and a second testing section, said first testing section including, first memory means having a memory area for row addresses of a target memory, the first memory means storing row addresses of defective bits of the target memory, second memory means having a memory area for column addresses of the target memory, for storing column addresses of defective bits of the target memory, first counter means for counting a number of defective-bit containing rows of the target memory, second counter means for counting a number of defective-bit containing columns of the target memory, third memory means for storing a number of rows of spare memory cells provided in the redundance circuit, fourth memory means for storing a number of columns of spare memory cells provided in the redundance circuit, first comparator means for comparing a count value of said first counter means with a number of rows stored in said third memory means, second comparator means for comparing a count value of said second counter means with a number of columns stored in said fourth memory means, and logical product means for acquiring a logical product of comparison outputs of said first and second comparator means and outputting a repair enable signal representing a repairable state, said second testing section including, fifth memory means for address failure, having at least a same memory area as the target memory, for storing defect information, third counter means for counting a number of defective-bit rows based on the defect information stored in said fifth memory means, fourth counter means for counting a number of defective-bit columns based on said defect information stored in said fifth memory means, sixth memory means for storing row addresses of defective bits of the target memory, with a number of defective bits present in the same row being taken as an address, and seventh memory means for storing column addresses of defective bits of the target memory, with a number of defective bits present in the same column being taken as an address, wherein when the repair enable signal is output from said logical product means in said first testing section and memory cells in at least one of a defective-bit containing row and a defective-bit containing column in the target memory can be replaced with spare memory cells in at least one of an associated row and an associated column in the redundancy circuit, memory cells in the defective-bit containing at least one of row and column in the target memory are replaced with memory cells in at least one of the associated row and associated column in the redundance circuit, based on the row addresses of defective bits stored in said first memory means and the column addresses of defective bits stored in said second memory means, and when defective memory cells in the target memory can be replaced with spare memory cells both in an associated row and an associated column in the redundance circuit, the defective memory cells both in a defective-bit containing row and a defective-bit containing column in the target memory are replaced with the spare memory cells in the redundance circuit, based on the row addresses of defective bits stored in said sixth memory means and the column addresses of defective bits stored in said seventh memory means in said second testing section.

Claim 14

A testing apparatus for testing a memory IC having a redundance circuit, comprising: a first testing section and a second testing section, said first testing section including, first memory means having a memory area for row addresses of a target memory, the first memory means storing row addresses of defective bits of the target memory, second memory means having a memory area for column addresses of the target memory, for storing column addresses of defective bits of the target memory, first counter means for counting a number of defective-bit containing rows of the target memory, second counter means for counting a number of defective-bit containing columns of the target memory, third memory means for storing a number of rows of spare memory cells provided in the redundance circuit, fourth memory means for storing a number of columns of spare memory cells provided in the redundance circuit, first comparator means for comparing a count value of said first counter means with a number of rows stored in said third memory means, second comparator means for comparing a count value of said second counter means with a number of columns stored in said fourth memory means, and logical product means for acquiring a logical product of comparison outputs of said first and second comparator means and outputting a repair enable signal representing a repairable state, said second testing section including, fifth memory means for address failure, having at least a same memory area as the target memory, for storing defect information, third counter means for counting a number of defective-bit rows based on the defect information stored in said fifth memory means, fourth counter means for counting a number of defective-bit columns based on said defect information stored in said fifth memory means, sixth memory means for storing row addresses of defective bits of the target memory, with a number of defective bits present in the same row being taken as an address, and seventh memory means for storing column addresses of defective bits of the target memory, with a number of defective bits present in the same column being taken as an address, wherein when the repair enable signal is output from said logical product means in said first testing section and memory cells in at least one of a defective-bit containing row and a defective-bit containing column in the target memory can be replaced with spare memory cells in at least one of an associated row and an associated column in the redundancy circuit, memory cells in the defective-bit containing at least one of row and column in the target memory are replaced with memory cells in at least one of the associated row and associated column in the redundance circuit, based on the row addresses of defective bits stored in said first memory means and the column addresses of defective bits stored in said second memory means, and when defective memory cells in the target memory can be replaced with spare memory cells both in an associated row and an associated column in the redundance circuit, the defective memory cells both in a defective-bit containing row and a defective-bit containing column in the target memory are replaced with the spare memory cells in the redundance circuit, based on the row addresses of defective bits stored in said sixth memory means and the column addresses of defective bits stored in said seventh memory means in said second testing section.

Claim 15

A testing apparatus according to claim 10, further comprising: pattern generator means for generating and supplying an address signal and data for test to the target memory; third comparator means for comparing data read out from the target memory with said data from said pattern generator means; and control means for receiving an output of said third comparator means and the address signal from said pattern generator means, and performing control to write data to said first memory means, said second memory means, said sixth memory means and said seventh memory means when the data read out from the target memory differs from the data from said pattern generator means.

Claim 16

A testing apparatus for testing a memory IC having a redundance circuit, comprising: first memory means having a memory area for column addresses of a target memory for storing column addresses of defective bits of the target memory; counter means for counting a number of defective-bit containing columns of the target memory; second memory means for storing a number of columns of spare memory cells provided in the redundance circuit; and first comparator means for comparing a count value of said counter means with a number of columns stored in said second memory means, wherein when the count value of said counter means exceeds the number of columns of spare memory cells stored in said second memory means, a test is terminated because the target memory is judged as unrepairable when the count value does not exceed the number of columns of spare memory cells stored in said second memory means, memory cells in a defective-bit containing column in the target memory are replaced with memory cells in an associated column in the redundance circuit based on the column addresses stored in said first memory means.

Claim 17

A testing apparatus for testing a memory IC having a redundance circuit, comprising: first memory means having a memory area for column addresses of a target memory for storing column addresses of defective bits of the target memory; counter means for counting a number of defective-bit containing columns of the target memory; second memory means for storing a number of columns of spare memory cells provided in the redundance circuit; and first comparator means for comparing a count value of said counter means with a number of columns stored in said second memory means, wherein when the count value of said counter means exceeds the number of columns of spare memory cells stored in said second memory means, a test is terminated because the target memory is judged as unrepairable when the count value does not exceed the number of columns of spare memory cells stored in said second memory means, memory cells in a defective-bit containing column in the target memory are replaced with memory cells in an associated column in the redundance circuit based on the column addresses stored in said first memory means.

Claim 18

A testing apparatus according to claim 12, further comprising: pattern generator means for generating and supplying an address signal and data for test to the target memory, said pattern generator means being disabled when said first comparator means outputs a signal representing an unrepairable state; second comparator means for comparating data read out from the target memory with the data from said pattern generator means; and control means for receiving an output of said second comparator means and the address signal from said pattern generator means, and performing control to write column addresses of defective bits in said first memory means when the data read out from the target memory differs from said data from said pattern generator means.

Claim 19

A testing apparatus according to claim 12, further comprising third memory means having a memory area for column addresses of the target memory, for storing presence of defective bits in the target memory, said counter means being counted up when defect information is written in said third memory means.