Voltage regulating integrated circuit

Claim 2

A circuit, comprising: a current source, connected to pull up a reference node; a first bipolar transistor, connected to pull down said reference node; second and third bipolar transistors, each connected to be operated at a substantially constant respective current, said second and third transistors having different respective emitter current densities; a first resistor, connected with said second and third transistors in such relation that the voltage drop across said resistor corresponds to the difference between the respective base-emitter voltages of said second and third transistors; a fourth bipolar transistor, having a base which is operatively connected to be driven by a sum of said voltage drop across said first resistor with at least one forward-biased-junction-voltage, and having an emitter which is operatively connected to drive the base of said first transistor; a second resistor, connected between said emitter of said fourth transistor and ground, and an additional resistor, connected between a base terminal of said third transistor and ground.

Claim 3

The circuit of claim 1, wherein said first and fourth transistors have equal active areas.

Claim 4

The circuit of claim 1, wherein said second transistor has more than five times as much active area as said third transistor.

Claim 5

The circuit of claim 1, wherein said second transistor has approximately ten times as much active area as said third transistor.

Claim 6

The circuit of claim 1, wherein the emitter of said first transistor is directly connected to ground, without any intervening resistor or active device.

Claim 7

The circuit of claim 1, wherein the emitter of said first transistor is directly connected to ground without any intervening resistor or active device, and the collector of said first transistor is directly connected to said reference node without any intervening resistor or active device.

Claim 8

The circuit of claim 1, wherein the collector of said first transistor is directly connected to said reference node, without any intervening resistor or active device.

Claim 9

The circuit of claim 1, wherein the collector of said first transistor is directly connected to said reference node, without any intervening resistor or active device.

Claim 10

The circuit of claim 1, further comprising a current mirror circuit which is connected to provide said current source; and further comprising an additional transistor which is connected to be driven by said reference node, and which is connected to source current to an external precision resistor, and which is connected to sink current from an input to said current mirror.

Claim 11

The circuit of claim 1, wherein each said bipolar transistor is an NPN transistor.

Claim 12

A circuit, comprising: a current source, connected to pull up a reference node; a first bipolar transistor, connected to pull down said reference node; second and third bipolar transistors, said second transistor having an active area which is at least about three times as large as the active area of said third transistor, and a first resistor interposed between the emitter of said second transistor and the emitter of said third transistor; said second and third transistors having respective base terminals operatively connected together; a fourth bipolar transistor, having a base which is operatively connected to be driven by the collector of said second transistor, and having an emitter which is operatively connected to drive the base of said first transistor; a second resistor, connected between said emitter of said fourth transistor and ground; a third resistor connected between said emitter of said third transistor and said reference node, and a fourth resistor connected between said emitter of said second transistor and said reference node.

Claim 13

A circuit, comprising: a current source, connected to pull up a reference node; a first bipolar transistor, connected to pull down said reference node; second and third bipolar transistors, said second transistor having an active area which is at least about three times as large as the active area of said third transistor, and a first resistor interposed between the emitter of said second transistor and the emitter of said third transistor; said second and third transistors having respective base terminals operatively connected together; a fourth bipolar transistor, having a base which is operatively connected to be driven by the collector of said second transistor, and having an emitter which is operatively connected to drive the base of said first transistor; a second resistor, connected between said emitter of said fourth transistor and ground; a third resistor connected between said emitter of said third transistor and said reference node, and a fourth resistor connected between said emitter of said second transistor and said reference node.

Claim 14

The circuit of claim 11, wherein said first and fourth transistors have equal active areas.

Claim 15

The circuit of claim 11, wherein said second transistor has more than five times as much active area as said third transistor.

Claim 16

The circuit of claim 11, wherein said second transistor has approximately ten times as much active area as said third transistor.

Claim 17

The circuit of claim 11, wherein the emitter of said first transistor is directly connected to ground, without any intervening resistor or active device.

Claim 18

The circuit of claim 11, wherein the emitter of said first transistor is directly connected to ground without any intervening resistor or active device, and the collector of said first transistor is directly connected to said reference node without any intervening resistor or active device.

Claim 19

The circuit of claim 11, wherein the collector of said first transistor is directly connected to said reference node, without any intervening resistor or active device.

Claim 20

The circuit of claim 11, wherein the collector of said first transistor is directly connected to said reference node, without any intervening resistor or active device.

Claim 21

The circuit of claim 11, further comprising a current mirror circuit which is connected to provide said current source, and further comprising an additional transistor which is connected to be driven by said reference node, and which is connected to source current to an external precision resistor, and which is connected to sink current from an input to said current mirror.

Claim 22

The circuit of claim 11, wherein each said bipolar transistor is an NPN transistor.

Claim 23

A circuit, comprising: a current source, connected to pull up a reference node; a first bipolar transistor, connected to pull down said reference node; second and third bipolar transistors, said second transistor having an active area which is at least about three times as large as the active area of said third transistor, and a first resistor interposed between the emitter of said second transistor and the emitter of said third transistor; a fourth bipolar transistor, having a base which is operatively connected to be driven by the collector of said second transistor, and having an emitter which is operatively connected to drive the base of said first transistor; a second resistor, connected between said emitter of said fourth transistor and ground; a third resistor connected between said emitter of said third transistor and said reference node, and a fourth resistor connected between said emitter of said second transistor and said reference node; said second and third bipolar transistors having respective base terminals both operatively connected to be pulled up by a fifth transistor and to be pulled down by a fifth resistor which is substantially equal in value to said second resistor.

Claim 24

A circuit, comprising: a current source, connected to pull up a reference node; a first bipolar transistor, connected to pull down said reference node; second and third bipolar transistors, said second transistor having an active area which is at least about three times as large as the active area of said third transistor, and a first resistor interposed between the emitter of said second transistor and the emitter of said third transistor; a fourth bipolar transistor, having a base which is operatively connected to be driven by the collector of said second transistor, and having an emitter which is operatively connected to drive the base of said first transistor; a second resistor, connected between said emitter of said fourth transistor and ground; a third resistor connected between said emitter of said third transistor and said reference node, and a fourth resistor connected between said emitter of said second transistor and said reference node; said second and third bipolar transistors having respective base terminals both operatively connected to be pulled up by a fifth transistor and to be pulled down by a fifth resistor which is substantially equal in value to said second resistor.

Claim 25

The circuit of claim 21, wherein said first and fourth transistors have equal active areas.

Claim 26

The circuit of claim 21, wherein said second transistor has more than five times as much active area as said third transistor.

Claim 27

The circuit of claim 21, wherein said second transistor has approximately ten times as much active area as said third transistor.

Claim 28

The circuit of claim 21, wherein the emitter of said first transistor is directly connected to ground, without any intervening resistor or active device.

Claim 29

The circuit of claim 21, wherein the emitter of said first transistor is directly connected to ground without any intervening resistor or active device, and the collector of said first transistor is directly connected to said reference node without any intervening resistor or active device.

Claim 30

The circuit of claim 21, wherein the collector of said first transistor is directly connected to said reference node, without any intervening resistor or active device.

Claim 31

The circuit of claim 21, wherein the collector of said first transistor is directly connected to said reference node, without any intervening resistor or active device.

Claim 32

The circuit of claim 21, further comprising a current mirror circuit which is connected to provide said current source; and further comprising an additional transistor which is connected to be driven by said reference node, and which is connected to source current to an external precision resistor, and which is connected to sink current from an input to said current mirror.

Claim 33

The circuit of claim 21, wherein each said bipolar transistor is an NPN transistor.

Claim 34

An integrated circuit, comprising: a current source, connected to source current to a reference node; first, second, third, and fourth NPN transistors, all operatively connected to sink current from said reference node to a ground node; said second and third transistors being connected to operate at significantly different current densities; said first through fourth transistors being connected in such relation that the potential of said reference node is equal to the base-emitter voltage of said first transistor plus the base-emitter voltage of said first transistor plus the base-emitter voltage of said fourth transistor plus a voltage which is proportional to the difference between the base-emitter voltages of said respective second and third transistors; wherein the emitter of said first transistor is directly connected to ground without any interventing resistor or active device, and the collector of said first transistor is directly connected to said reference node without any intervening resistor or active device; and further comprising a resistor, connected in parallel with the base-emitter junction of said first transistor.

Claim 35

An integrated circuit, comprising: a current source, connected to source current to a reference node; first, second, third, and fourth NPN transistors, all operatively connected to sink current from said reference node to a ground node; said second and third transistors being connected to operate at significantly different current densities; said first through fourth transistors being connected in such relation that the potential of said reference node is equal to the base-emitter voltage of said first transistor plus the base-emitter voltage of said first transistor plus the base-emitter voltage of said fourth transistor plus a voltage which is proportional to the difference between the base-emitter voltages of said respective second and third transistors; wherein the emitter of said first transistor is directly connected to ground without any interventing resistor or active device, and the collector of said first transistor is directly connected to said reference node without any intervening resistor or active device; and further comprising a resistor, connected in parallel with the base-emitter junction of said first transistor.

Claim 36

The integrated circuit of claim 31, wherein said first and fourth transistors have equal active areas.

Claim 37

The integrated circuit of claim 31, wherein said second transistor has approximately ten times as much active area as said third transistor.

Claim 38

The integrated circuit of claim 31, wherein the emitter of said first transistor is directly connected to ground without any intervening resistor or active device, and the collector of said first transistor is directly connected to said reference node without any intervening resistor or active device.

Claim 39

An integrated circuit, comprising: a first transistor having collector and emitter terminals connected between a voltage node and ground, a second transistor having a base terminal and a collector terminal thereof connected together, and an the emitter connected to provide an output, a resistor connected between said emitter and base of said first transistor, said base being also connected to the emitter of a third transistor having a collector thereof connected to said voltage node and a base thereof connected to said voltage node through a second resistor and to the collector of a fourth transistor, a further resistor between ground and the base of the fourth transistor whose emitter is grounded through a resistor fifth and sixth transistors connected together, with the base of the fifth transistor being connected to the emitter of the sixth and the base of said sixth transistor connected to the collector of the fifth transistor and connected in the circuit with the emitter of the fifth transistor connected to ground, the emitter of the sixth transistor being connected to the base of the fourth transistor, and the collector of said fourth transistor being connected to said voltage node, and the collector of said sixth transistor being connected to said voltage node through a resistor.

Claim 40

An integrated circuit, comprising: a first transistor having collector and emitter terminals connected between a voltage node and ground, a second transistor having a base terminal and a collector terminal thereof connected together, and an the emitter connected to provide an output, a resistor connected between said emitter and base of said first transistor, said base being also connected to the emitter of a third transistor having a collector thereof connected to said voltage node and a base thereof connected to said voltage node through a second resistor and to the collector of a fourth transistor, a further resistor between ground and the base of the fourth transistor whose emitter is grounded through a resistor fifth and sixth transistors connected together, with the base of the fifth transistor being connected to the emitter of the sixth and the base of said sixth transistor connected to the collector of the fifth transistor and connected in the circuit with the emitter of the fifth transistor connected to ground, the emitter of the sixth transistor being connected to the base of the fourth transistor, and the collector of said fourth transistor being connected to said voltage node, and the collector of said sixth transistor being connected to said voltage node through a resistor.

Claim 41

The integrated circuit of claim 35, wherein said collector of said second transistor is connected to an input of a current-mirror circuit effective to reproduce on plural outputs current values which are identical with or proportional to the one present on said collector.

Claim 42

The integrated circuit of claim 35, wherein the subcircuit defined by said first and third transistors with associated resistors corresponds structurally to the subcircuit which includes the fourth and sixth transistors and associated resistors.