Comma code generator

Claim 3

The apparatus according to claim 1 wherein the means for selectively inverting comprises an address calculator for determining which of the plurality of single bit storage elements to invert.

Claim 4

The apparatus according to claim 1 further comprising means for transmitting a m+1 bit comma code word output to a receiving circuit.

Claim 5

The apparatus according to claim 3 further comprising means for concatenating two or more m+1 bit code words, where m is a variable based upon the data value m, for forming comma codes longer than M bits.

Claim 6

A comma code generator comprising: a. a shift device having an N bit barrel shifter coupled to a register, the register having a plurality of bit storage elements coupled to receive an m+1 bit comma code word, the device comprising: (1) means for receiving an m value data word; and (2) means for selectively inverting a logic state of an appropriate one of the bit storage elements determined in relation to m; b. first buffer storage means for receiving a first portion of the N bits in the barrel shifter comprising an M bit storage having an M bit output word and wherein M<N; c. second buffer storage means for receiving a second portion of the N bits in the barrel shifter comprising A remainder bits wherein A=N-M; d. means for transmitting the M bit output word to a receiving apparatus; and e. means for subsequently transmitting the A remainder bits to the means for receiving.

Claim 7

A comma code generator comprising: a. a shift device having an N bit barrel shifter coupled to a register, the register having a plurality of bit storage elements coupled to receive an m+1 bit comma code word, the device comprising: (1) means for receiving an m value data word; and (2) means for selectively inverting a logic state of an appropriate one of the bit storage elements determined in relation to m; b. first buffer storage means for receiving a first portion of the N bits in the barrel shifter comprising an M bit storage having an M bit output word and wherein M<N; c. second buffer storage means for receiving a second portion of the N bits in the barrel shifter comprising A remainder bits wherein A=N-M; d. means for transmitting the M bit output word to a receiving apparatus; and e. means for subsequently transmitting the A remainder bits to the means for receiving.

Claim 8

The apparatus according to claim 5 wherein the means for subsequently transmitting the A remainder bits comprises means for transmitting the A remainder bits to the first buffer storage means.

Claim 9

The apparatus according the claim 6 further comprising a multiplexer coupled to receive the M bit output word from the first buffer storage means and to receive the A remainder bits from the second buffer storage means.

Claim 10

A comma code generator comprising: a. means for receiving a data word having a data value m; b. an address calculator coupled to receive the data value m and calculating an address; and c. a memory array of bit storage elements arranged to have an M bit output word, the array being coupled to receive the address from the address calculator, the array comprising: (1) means for initializing the bit storage elements to a first logic state; and (2) means for selectively inverting the logic state of an appropriate one of the bit storage elements selected according to the address.

Claim 11

A comma code generator comprising: a. means for receiving a data word having a data value m; b. an address calculator coupled to receive the data value m and calculating an address; and c. a memory array of bit storage elements arranged to have an M bit output word, the array being coupled to receive the address from the address calculator, the array comprising: (1) means for initializing the bit storage elements to a first logic state; and (2) means for selectively inverting the logic state of an appropriate one of the bit storage elements selected according to the address.

Claim 12

The apparatus according to claim 8 wherein the address calculator further comprises: a. means for storing a previous address; b. means for adding the previous address to the data value m for forming a result; and c. means for incrementing the result.

Claim 15

The method according to claim 10 further comprising the step of transmitting the M bit code word output to a receiving circuit.

Claim 16

The method according to claim 11 further comprising the step of concatenating two or more m+1 bit code words, where m is a variable based upon the data value m for forming comma codes longer than M bits.

Claim 17

The method according to claim 10 further comprising the steps of: a. storing a previous address; b. adding the previous address to the data value m for forming a result; and c. incrementing the result.