Character display device for synchronizing operation of video ram to operation of CPU

Claim 1

In a character display device for displaying characters on a television screen, the improvement comprising: a CPU which executes a series of processing steps in sequence according to machine cycles, each machine cycle being made up of a first portion coincident with a first plurality of clock periods and a second portion coincident with a second plurality of clock periods: first address signal generation means for generating a first address signal in response to CPU operation timing: second address signal generation means for generating a second address signal in synchronization with horizontal scanning and vertical scanning of television signals; address change means coupled to said first address signal generation means and said second address signal generation means and controlled according to clock periods of the machine cycles for alternately outputting the first address signal during the first portion of one machine cycle and selectively outputting said second address signal during the second portion of the one machine cycle; a video RAM being accessed according to said first or second address signal output from said address change means in synchronism with clock periods of the machine cycles, said video RAM having data for character display on the television screen written therein or read therefrom; and television signal generation means for generating television signals to display characters on the television screen in response to data read from said video RAM.