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US5343431A
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Semiconductor memory apparatus, test apparatus therefor and method for relieving semiconductor memory apparatus from short circuit
Assignee: Renesas Electronics Corp
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Filing: 1993-04-06
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Granted: 1994-08-30
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Expires: 2013-04-06
Abstract
Abstract A semiconductor memory apparatus capable of judging whether or not there is short circuit between bit lines 1 (word lines) by respectively connecting a plurality of the bit lines 1 (word lines), wired in parallel to each other so as to select memory cell for outputting data from a memory cell array 4 in which memory cells are arranged in the form of matrix, connected to power source potential line 14 and ground potential line 16 alternately through switching elements 5, 6 respectively, thereby measuring leak current flowing between the both lines 14 and 16 in the state where the switching elements 5, 6 are ON, a testing apparatus being provided with a power source 10 supplying to each of the switching elements 5, 6 of this semiconductor memory apparatus and with an ampere meter 11 for measuring leak current, and relieving method for the semiconductor memory apparatus from short circuit between the bit lines (word lines) by making the switching elements 5, 6 ON as well as applying overvoltage to the bit lines (word lines) from the power source 10, thereby generating Joule heat at foreign matter which short-circuits between adjacent bit lines 1 (word lines) so as to burn off the foreign matter by the Joule heat.
Inventors
- 👤 Takahiro Ohtsuka
- 👤 Shozo Shirota
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:19
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/88; G11C29/02; G11C29/025; G11C29/04; G11C29/50; G11C7/00; G11C7/12; G11C2029/5006
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
156 words
A semiconductor memory apparatus, comprising: a memory cell array in which memory cells are arranged in the form of matrix in column direction × row direction; a plurality of column direction memory cell select lines each which is commonly connected to memory cells of each column of said memory cell array; and a plurality of row direction memory cell select lines each which is commonly connected to memory cells of each row of said memory cell array; wherein data is read out from the memory cell which is commonly selected by one of said column direction memory cell select line and one of said row direction memory cell select line, further comprising a plurality of switching elements which are disposed to connect adjacent ones of said column direction memory cell select lines and/or adjacent ones of said row direction memory cell select lines successively to a power source potential line and a ground potential line respectively.
Claim 2
Dependent Claim
156 words
A semiconductor memory apparatus, comprising: a memory cell array in which memory cells are arranged in the form of matrix in column direction × row direction; a plurality of column direction memory cell select lines each which is commonly connected to memory cells of each column of said memory cell array; and a plurality of row direction memory cell select lines each which is commonly connected to memory cells of each row of said memory cell array; wherein data is read out from the memory cell which is commonly selected by one of said column direction memory cell select line and one of said row direction memory cell select line, further comprising a plurality of switching elements which are disposed to connect adjacent ones of said column direction memory cell select lines and/or adjacent ones of said row direction memory cell select lines successively to a power source potential line and a ground potential line respectively.
Claim 3
Dependent Claim
30 words
A semiconductor memory apparatus as set forth in claim 1, wherein said power source potential line and ground potential line are connected to an independent power source for exclusive use.
Claim 4
Dependent Claim
132 words
A semiconductor memory apparatus, comprising: a memory cell array in which memory cells are arranged in the form of matrix in column direction × row direction; a plurality of bit lines each which is commonly connected to memory cells of each column of said memory cell array; and a plurality of word lines each which is commonly connected to memory cells of each row of said memory cell array; wherein data is read out from the memory cell which is commonly selected by one of said bit lines and one of said word lines, further comprising a plurality of switching elements which are disposed to connect adjacent ones of said bit lines and/or adjacent ones of said word lines successively to a power source potential line and a ground potential line respectively.
Claim 5
Dependent Claim
132 words
A semiconductor memory apparatus, comprising: a memory cell array in which memory cells are arranged in the form of matrix in column direction × row direction; a plurality of bit lines each which is commonly connected to memory cells of each column of said memory cell array; and a plurality of word lines each which is commonly connected to memory cells of each row of said memory cell array; wherein data is read out from the memory cell which is commonly selected by one of said bit lines and one of said word lines, further comprising a plurality of switching elements which are disposed to connect adjacent ones of said bit lines and/or adjacent ones of said word lines successively to a power source potential line and a ground potential line respectively.
Claim 6
Dependent Claim
31 words
A semiconductor memory apparatus as set forth in claim 3, wherein said power source potential line and said ground potential line are connected to an independent power source for exclusive use.
Claim 7
Dependent Claim
245 words
A testing apparatus for detecting short circuit between adjacent memory cell select lines of column direction memory cell select lines and/or row direction memory cell select lines of a semiconductor memory apparatus, said semiconductor memory apparatus comprising: a memory cell array in which memory cells are arranged in the form of matrix in column direction × row direction; a plurality of column direction memory cell select lines each which is commonly connected to memory cells of each column of said memory cell array; a plurality of row direction memory cell select lines each which is commonly connected to memory cells of each row of said memory cell array; and a plurality of switching elements which are disposed to connect said respective column direction memory cell select lines and/or said row direction memory cell select lines successively to a power source potential line and a ground potential line alternatively, wherein data is read out from the memory cell which is commonly selected by one of said column direction memory cell select line and one of said row direction memory cell select line, comprising: a power source connected to said power source potential line and said ground potential line; a control signal line making said each of said switching elements ON/OFF at the same time, and a current measuring apparatus which measures current flowing between said power source potential line and said ground potential line in the case where said each of said switching elements is ON.
Claim 8
Dependent Claim
245 words
A testing apparatus for detecting short circuit between adjacent memory cell select lines of column direction memory cell select lines and/or row direction memory cell select lines of a semiconductor memory apparatus, said semiconductor memory apparatus comprising: a memory cell array in which memory cells are arranged in the form of matrix in column direction × row direction; a plurality of column direction memory cell select lines each which is commonly connected to memory cells of each column of said memory cell array; a plurality of row direction memory cell select lines each which is commonly connected to memory cells of each row of said memory cell array; and a plurality of switching elements which are disposed to connect said respective column direction memory cell select lines and/or said row direction memory cell select lines successively to a power source potential line and a ground potential line alternatively, wherein data is read out from the memory cell which is commonly selected by one of said column direction memory cell select line and one of said row direction memory cell select line, comprising: a power source connected to said power source potential line and said ground potential line; a control signal line making said each of said switching elements ON/OFF at the same time, and a current measuring apparatus which measures current flowing between said power source potential line and said ground potential line in the case where said each of said switching elements is ON.
Claim 9
Dependent Claim
30 words
A testing apparatus as set forth in claim 5, wherein said power source potential line and said ground potential line are connected to the independent power source for exclusive use.
Claim 10
Dependent Claim
208 words
A testing apparatus for detecting short circuit between adjacent bit lines and/or word lines of a semiconductor memory apparatus, said semiconductor memory apparatus comprising: a memory cell array in which memory cells are arranged in the form of matrix in column direction × row direction; a plurality of bit lines each which is commonly connected to memory cells of each column of said memory cell array; a plurality of word lines each which is commonly connected to memory cells of each row of said memory cell array; and a plurality of switching elements which are disposed to connect said respective bit lines and/or said word lines successively to a power source potential line and a ground potential line alternately, wherein data is read out from the memory cell which is commonly selected by one of said bit line and one of said word line, comprising: a power source connected to said power source potential line and said ground potential line; a control signal line making said each of said switching elements ON/OFF at the same time; and a current measuring apparatus which measures current flowing between said power source potential line and said ground potential line in the case where said each of said switching elements is ON.
Claim 11
Dependent Claim
208 words
A testing apparatus for detecting short circuit between adjacent bit lines and/or word lines of a semiconductor memory apparatus, said semiconductor memory apparatus comprising: a memory cell array in which memory cells are arranged in the form of matrix in column direction × row direction; a plurality of bit lines each which is commonly connected to memory cells of each column of said memory cell array; a plurality of word lines each which is commonly connected to memory cells of each row of said memory cell array; and a plurality of switching elements which are disposed to connect said respective bit lines and/or said word lines successively to a power source potential line and a ground potential line alternately, wherein data is read out from the memory cell which is commonly selected by one of said bit line and one of said word line, comprising: a power source connected to said power source potential line and said ground potential line; a control signal line making said each of said switching elements ON/OFF at the same time; and a current measuring apparatus which measures current flowing between said power source potential line and said ground potential line in the case where said each of said switching elements is ON.
Claim 12
Dependent Claim
30 words
A testing apparatus as set forth in claim 7, wherein said power source potential line and said ground potential line are connected to the independent power source for exclusive use.
Claim 13
Independent Claim
243 words
A method for relieving a semiconductor memory apparatus from short circuit between adjacent memory cell select lines of column direction memory cell select lines and/or row direction memory cell select lines of a semiconductor memory apparatus, said semiconductor memory apparatus comprising: a memory cell array in which memory cells are arranged in the form of matrix in column direction × row direction; a plurality of column direction memory cell select lines each which is commonly connected to memory cells of each column of said memory cell array; a plurality of row direction memory cell select lines each which is commonly connected to memory cells of each row of said memory cell array; and a plurality of switching elements which are disposed to connect said respective column direction memory cell select lines and/or said row direction memory cell select lines successively to a power source potential line and a ground potential line alternatively, wherein data is read out from the memory cell which is commonly selected by one of said column direction memory cell select line and one of said row direction memory cell select line, comprising steps of: connecting said power source potential line and said ground potential line to the power source; making each of said switching elements ON by said control signal; and applying overvoltage to said memory cell select lines to burn off foreign matter which short-circuit between adjacent memory cell select lines by Joule heat according to said overvoltage.
Claim 14
Independent Claim
243 words
A method for relieving a semiconductor memory apparatus from short circuit between adjacent memory cell select lines of column direction memory cell select lines and/or row direction memory cell select lines of a semiconductor memory apparatus, said semiconductor memory apparatus comprising: a memory cell array in which memory cells are arranged in the form of matrix in column direction × row direction; a plurality of column direction memory cell select lines each which is commonly connected to memory cells of each column of said memory cell array; a plurality of row direction memory cell select lines each which is commonly connected to memory cells of each row of said memory cell array; and a plurality of switching elements which are disposed to connect said respective column direction memory cell select lines and/or said row direction memory cell select lines successively to a power source potential line and a ground potential line alternatively, wherein data is read out from the memory cell which is commonly selected by one of said column direction memory cell select line and one of said row direction memory cell select line, comprising steps of: connecting said power source potential line and said ground potential line to the power source; making each of said switching elements ON by said control signal; and applying overvoltage to said memory cell select lines to burn off foreign matter which short-circuit between adjacent memory cell select lines by Joule heat according to said overvoltage.
Claim 15
Dependent Claim
33 words
A method for relieving semiconductor memory apparatus as set forth in claim 9, wherein said power source potential line and ground potential line are connected to the independent power source for exclusive use.
Claim 16
Independent Claim
208 words
A method for relieving a semiconductor memory apparatus from short circuit between adjacent bit lines and/or word lines of a semiconductor memory apparatus, said semiconductor memory apparatus comprising: a memory cell array in which memory cells are arranged in the form of matrix in column direction × row direction; a plurality of bit lines each which is commonly connected to memory cells of each column of said memory cell array; a plurality of word lines each which is commonly connected to memory cells of each row of said memory cell array; and a plurality of switching elements which are disposed to connect said respective bit lines and/or said word lines successively to a power source potential line and a ground potential line alternately, wherein data is read out from the memory cell which is commonly selected by one of said bit line and one of said word line, comprising steps of: connecting said power source potential line and said ground potential line to the power source; making each of said switching elements ON by said control signal; and applying overvoltage to said bit lines and/or word lines to burn off foreign matter which short-circuits between adjacent bit lines and/or word lines by Joule heat according to said overvoltage.
Claim 17
Independent Claim
208 words
A method for relieving a semiconductor memory apparatus from short circuit between adjacent bit lines and/or word lines of a semiconductor memory apparatus, said semiconductor memory apparatus comprising: a memory cell array in which memory cells are arranged in the form of matrix in column direction × row direction; a plurality of bit lines each which is commonly connected to memory cells of each column of said memory cell array; a plurality of word lines each which is commonly connected to memory cells of each row of said memory cell array; and a plurality of switching elements which are disposed to connect said respective bit lines and/or said word lines successively to a power source potential line and a ground potential line alternately, wherein data is read out from the memory cell which is commonly selected by one of said bit line and one of said word line, comprising steps of: connecting said power source potential line and said ground potential line to the power source; making each of said switching elements ON by said control signal; and applying overvoltage to said bit lines and/or word lines to burn off foreign matter which short-circuits between adjacent bit lines and/or word lines by Joule heat according to said overvoltage.
Claim 18
Dependent Claim
34 words
A method for relieving semiconductor memory apparatus as set forth in claim 10, wherein said power source potential line and said ground potential line are connected to the independent power source for exclusive use.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-29 | 1998-02-28 | 1998-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-29 | 2002-02-28 | 2002-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-29 | 2006-02-28 | 2006-08-30 | $7700.00 | Window Closed / Lapsed |