Ferroelectric memory cell arrangement having a split capacitor plate structure

Claim 1

A method for fabricating a ferroelectric memory, comprising the steps of: forming a pair of select transistors in a semiconductor material, each said transistor having a drain region and a source region; forming a ferroelectric capacitor structure comprising two distinct ferroelectric capacitors overlying said pair of transistors, including forming a top plate, a bottom plate and a ferroelectric material therebetween, further including forming one of said capacitor plates with a layer of a conductive material having two plates laterally spaced apart and isolated from each other so as to define a pair of capacitor plates, and forming the other capacitor plate as a single plate that is vertically spaced from the pair of capacitor plates with the ferroelectric material disposed therebetween, said single capacitor plate being shared with both transistors; forming respective first level interconnect elements in contact with a drain region of each said transistor; forming respective second level interconnect elements that are different from said capacitor plates, in contact with said first level interconnect elements; forming said second level interconnect elements in contact with respect to said pair of capacitor plates; and forming a conductor in contact with the single capacitor plate that is not split.

Claim 2

A method for fabricating a ferroelectric memory, comprising the steps of: forming a pair of select transistors in a semiconductor material, each said transistor having a drain region and a source region; forming a ferroelectric capacitor structure comprising two distinct ferroelectric capacitors overlying said pair of transistors, including forming a top plate, a bottom plate and a ferroelectric material therebetween, further including forming one of said capacitor plates with a layer of a conductive material having two plates laterally spaced apart and isolated from each other so as to define a pair of capacitor plates, and forming the other capacitor plate as a single plate that is vertically spaced from the pair of capacitor plates with the ferroelectric material disposed therebetween, said single capacitor plate being shared with both transistors; forming respective first level interconnect elements in contact with a drain region of each said transistor; forming respective second level interconnect elements that are different from said capacitor plates, in contact with said first level interconnect elements; forming said second level interconnect elements in contact with respect to said pair of capacitor plates; and forming a conductor in contact with the single capacitor plate that is not split.

Claim 11

A method of fabricating a ferroelectric memory, comprising the steps of: forming a pair of MOS transistors in a semiconductor material, each said transistor having a drain region and a common source region; forming a respective word line in contact with a gate of each said transistor; forming a bit line in contact with said common source region; forming a first level refractory metal contact to the respective drain regions; forming an isolation layer isolating said first level metal; forming a pair of ferroelectric capacitors overlying said isolation layer and over said transistors, each said ferroelectric capacitor having a bottom plate, a ferroelectric dielectric and a top plate; forming respective second metal contacts for connecting one plate of each said capacitor to the respective first level metal to thereby connect one said ferroelectric capacitor to a respective transistor, the forming of the second metal contacts being carried out after forming a ferroelectric material into a ferroelectric dielectric; and forming a metal contact to the other plates of each said ferroelectric capacitor, said metal contact defining a drive line.

Claim 12

A method of fabricating a ferroelectric memory, comprising the steps of: forming a pair of MOS transistors in a semiconductor material, each said transistor having a drain region and a common source region; forming a respective word line in contact with a gate of each said transistor; forming a bit line in contact with said common source region; forming a first level refractory metal contact to the respective drain regions; forming an isolation layer isolating said first level metal; forming a pair of ferroelectric capacitors overlying said isolation layer and over said transistors, each said ferroelectric capacitor having a bottom plate, a ferroelectric dielectric and a top plate; forming respective second metal contacts for connecting one plate of each said capacitor to the respective first level metal to thereby connect one said ferroelectric capacitor to a respective transistor, the forming of the second metal contacts being carried out after forming a ferroelectric material into a ferroelectric dielectric; and forming a metal contact to the other plates of each said ferroelectric capacitor, said metal contact defining a drive line.

Claim 14

A method of fabricating a ferroelectric memory, comprising the steps of: forming a transistor in a semiconductor material; forming a first isolation layer over said transistor; forming a refractory interconnection through the first isolation layer in contact with a region of said transistor; forming a second isolation layer for isolating the refractory interconnection; forming a bottom capacitor plate at least partially overlying said transistor; forming a top capacitor plate and a ferroelectric dielectric between the top and bottom capacitor plate; sintering the ferroelectric material at a high temperature to form a polarizable dielectric; forming an intermediate nonrefractory interconnect plug of a conductive material after said ferroelectric sintering and forming said nonrefractory interconnect plug distinct from said refractory interconnection for connecting interconnection to said bottom capacitor plate is said bottom capacitor plate is electrically connected via said intermediate interconnect plug through the second isolation layer in contact with said refractory interconnection so that said bottom capacitor plate is electrically connected to the transistor; and forming a conductor in contact with said top capacitor plate.

Claim 15

A method of fabricating a ferroelectric memory, comprising the steps of: forming a transistor in a semiconductor material; forming a first isolation layer over said transistor; forming a refractory interconnection through the first isolation layer in contact with a region of said transistor; forming a second isolation layer for isolating the refractory interconnection; forming a bottom capacitor plate at least partially overlying said transistor; forming a top capacitor plate and a ferroelectric dielectric between the top and bottom capacitor plate; sintering the ferroelectric material at a high temperature to form a polarizable dielectric; forming an intermediate nonrefractory interconnect plug of a conductive material after said ferroelectric sintering and forming said nonrefractory interconnect plug distinct from said refractory interconnection for connecting interconnection to said bottom capacitor plate is said bottom capacitor plate is electrically connected via said intermediate interconnect plug through the second isolation layer in contact with said refractory interconnection so that said bottom capacitor plate is electrically connected to the transistor; and forming a conductor in contact with said top capacitor plate.

Claim 18

A method of fabricating a ferroelectric memory, comprising the steps of: forming a pair of transistors in a semiconductor material, said transistors having a common source region and different drain regions; forming an electrical isolation over said transistors; forming a first interconnection through said isolation in contact with one transistor drain region and a second interconnect through said isolation in contact with the other transistor drain region; forming a split bottom capacitor plate overlying said transistors, including forming a first split bottom plate in electrical contact with said first transistor interconnection and forming the second split bottom plate in electrical contact with the second transistor interconnection; forming one top capacitor plate overlying at least a portion of each said first and second split bottom plates and forming a ferroelectric material between the top capacitor plate and the split bottom capacitor plates; and forming a conductor in contact with said One top capacitor plate.

Claim 19

A method of fabricating a ferroelectric memory, comprising the steps of: forming a pair of transistors in a semiconductor material, said transistors having a common source region and different drain regions; forming an electrical isolation over said transistors; forming a first interconnection through said isolation in contact with one transistor drain region and a second interconnect through said isolation in contact with the other transistor drain region; forming a split bottom capacitor plate overlying said transistors, including forming a first split bottom plate in electrical contact with said first transistor interconnection and forming the second split bottom plate in electrical contact with the second transistor interconnection; forming one top capacitor plate overlying at least a portion of each said first and second split bottom plates and forming a ferroelectric material between the top capacitor plate and the split bottom capacitor plates; and forming a conductor in contact with said One top capacitor plate.

Claim 22

A method of fabricating a ferroelectric memory, comprising the steps of: forming a pair of MOS transistors in a semiconductor substrate, said transistors having a common source region and different drain regions; forming a different word line as a gate structure for each said transistor; forming a dielectric overlying said transistor pair; forming a first level metal and patterning the first level metal to define a first metal interconnect and a second metal interconnect through said dielectric and connected respectively to said different drain regions, and to define a third metal interconnect through said dielectric and connected to said common source region, said first, second and third interconnects being isolated from each other; forming a ferroelectric capacitor overlying said dielectric, including forming a top electrode and a bottom electrode with a ferroelectric dielectric therebetween, and forming one said top or bottom electrode as a split electrode to define two electrode conductors isolated from each other, the other electrode and ferroelectric dielectric being common thereto; forming said ferroelectric capacitor with lateral dimensions such that a lateral dimension of said bottom plate structure is wider than a lateral dimension of said ferroelectric material, and the lateral dimension of the ferroelectric material is wider than a corresponding lateral dimension of said top electrode; forming a second level metal and patterning the second level metal to interconnect one split electrode to the first metal interconnect, and patterning said second level metal to interconnect the other split electrode to the second metal interconnect; and passivating the ferroelectric memory.

Claim 23

A method of fabricating a ferroelectric memory, comprising the steps of: forming a pair of MOS transistors in a semiconductor substrate, said transistors having a common source region and different drain regions; forming a different word line as a gate structure for each said transistor; forming a dielectric overlying said transistor pair; forming a first level metal and patterning the first level metal to define a first metal interconnect and a second metal interconnect through said dielectric and connected respectively to said different drain regions, and to define a third metal interconnect through said dielectric and connected to said common source region, said first, second and third interconnects being isolated from each other; forming a ferroelectric capacitor overlying said dielectric, including forming a top electrode and a bottom electrode with a ferroelectric dielectric therebetween, and forming one said top or bottom electrode as a split electrode to define two electrode conductors isolated from each other, the other electrode and ferroelectric dielectric being common thereto; forming said ferroelectric capacitor with lateral dimensions such that a lateral dimension of said bottom plate structure is wider than a lateral dimension of said ferroelectric material, and the lateral dimension of the ferroelectric material is wider than a corresponding lateral dimension of said top electrode; forming a second level metal and patterning the second level metal to interconnect one split electrode to the first metal interconnect, and patterning said second level metal to interconnect the other split electrode to the second metal interconnect; and passivating the ferroelectric memory.

Claim 33

A method of fabricating a ferroelectric memory cell, comprising the steps of: forming a pair of MOS transistors in a semiconductor substrate, said transistors each having a drain region spaced apart from each other, a common source region located between the spaced apart drain regions, and a gate conductor; forming a first metal level as individual contacts to the transistor drain regions and the common source region; forming an electrical insulation for electrically isolating said individual contacts; forming one conductive plate overlying said common source that functions as a plate for two ferroelectric capacitors; forming a pair of second capacitor plates, each second capacitor plate being spaced vertically from said one conductive plate; forming a ferroelectric material between said one conductive plate and said pair of second capacitor plates, thereby defining the two ferroelectric capacitors; forming a drive line in contact with said one conductive plate for allowing a single drive signal to be coupled to both said ferroelectric capacitors; and forming an electrical connection between the respective pair of second capacitor plates and the transistor drain regions.

Claim 34

A method of fabricating a ferroelectric memory cell, comprising the steps of: forming a pair of MOS transistors in a semiconductor substrate, said transistors each having a drain region spaced apart from each other, a common source region located between the spaced apart drain regions, and a gate conductor; forming a first metal level as individual contacts to the transistor drain regions and the common source region; forming an electrical insulation for electrically isolating said individual contacts; forming one conductive plate overlying said common source that functions as a plate for two ferroelectric capacitors; forming a pair of second capacitor plates, each second capacitor plate being spaced vertically from said one conductive plate; forming a ferroelectric material between said one conductive plate and said pair of second capacitor plates, thereby defining the two ferroelectric capacitors; forming a drive line in contact with said one conductive plate for allowing a single drive signal to be coupled to both said ferroelectric capacitors; and forming an electrical connection between the respective pair of second capacitor plates and the transistor drain regions.