Patent US5354699A successfully refreshed from Google Patents.
US5354699A
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US
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Method of manufacturing semiconductor integrated circuit device
Assignee: Renesas Electronics Corp
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Filing: 1992-10-22
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Granted: 1994-10-11
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Expires: 2012-10-22
Abstract
Abstract Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
Inventors
- 👤 Takahide Ikeda
- 👤 Kouichirou Yamada
- 👤 Osamu Saito
- 👤 Masanori Odaka
- 👤 Nobuo Tamba
- 👤 Katsumi Ogiue
- 👤 Atsushi Hiraishi
- 👤 Atsuo Watanabe
- 👤 Mitsuru Hirao
- 👤 Akira Fukami
- 👤 Masayuki Ohayashi
- 👤 Tadashi Kuramoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:19
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/011; H10D64/0111; H10D64/0113; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; Y; Y10; Y10S; Y10S148/00; Y10S148/009
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
343 words
A method of manufacturing a semiconductor integrated circuit device having at least one bipolar transistor and at least one MISFET, comprising the steps of: a) forming a silicon film, by deposition, overlying first and second portions of a main surface of a semiconductor body, said first and second portions being portions in which said bipolar transistor and MISFET are to be formed, respectively; b) introducing first impurities of a first conductivity type into said silicon film overlying said first portion, and introducing second impurities of a second conductivity type, which is opposite to said first conductivity type, into said silicon film overlying said second portion, thereby to form a first silicon film part of said first conductivity type and a second silicon film part of said second conductivity type in said silicon film; c) forming a metal silicide layer on said silicon film, the metal silicide layer being formed by deposition of metal silicide, so as to cover said silicon film; d) after the steps a), b) and c), removing parts of said metal silicide layer so as to form a first metal silicide layer on said first silicon film part and a second metal silicide layer on said second silicon film part in such a manner that said first metal silicide layer on said first silicon film part and second metal silicide layer on said second silicon film part are spaced from each other; e) after the step d), forming a silicon oxide film over said main surface of said semiconductor body by chemical vapor deposition so as to cover said first metal silicide layer and said second metal silicide layer; and f) patterning said silicon oxide film, said first metal silicide layer, said second metal silicide layer, and said silicon film, by etching, so as to form a base lead-out electrode of said bipolar transistor comprised of said first silicon film part and said first metal silicide layer, and to form a gate electrode of said MISFET comprised of said second silicon film part and said second metal silicide layer, simultaneously.
Claim 2
Independent Claim
343 words
A method of manufacturing a semiconductor integrated circuit device having at least one bipolar transistor and at least one MISFET, comprising the steps of: a) forming a silicon film, by deposition, overlying first and second portions of a main surface of a semiconductor body, said first and second portions being portions in which said bipolar transistor and MISFET are to be formed, respectively; b) introducing first impurities of a first conductivity type into said silicon film overlying said first portion, and introducing second impurities of a second conductivity type, which is opposite to said first conductivity type, into said silicon film overlying said second portion, thereby to form a first silicon film part of said first conductivity type and a second silicon film part of said second conductivity type in said silicon film; c) forming a metal silicide layer on said silicon film, the metal silicide layer being formed by deposition of metal silicide, so as to cover said silicon film; d) after the steps a), b) and c), removing parts of said metal silicide layer so as to form a first metal silicide layer on said first silicon film part and a second metal silicide layer on said second silicon film part in such a manner that said first metal silicide layer on said first silicon film part and second metal silicide layer on said second silicon film part are spaced from each other; e) after the step d), forming a silicon oxide film over said main surface of said semiconductor body by chemical vapor deposition so as to cover said first metal silicide layer and said second metal silicide layer; and f) patterning said silicon oxide film, said first metal silicide layer, said second metal silicide layer, and said silicon film, by etching, so as to form a base lead-out electrode of said bipolar transistor comprised of said first silicon film part and said first metal silicide layer, and to form a gate electrode of said MISFET comprised of said second silicon film part and said second metal silicide layer, simultaneously.
Claim 3
Dependent Claim
109 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising: forming side wall insulators on side surfaces of said base lead-out electrode and said gate electrode, said side wall insulators on said side surfaces of said base lead-out electrode defining an emitter-forming region of said bipolar transistor, and said side wall insulators on said side surfaces of said gate electrode defining source- and drain-forming regions of said MISFET; and after the formation of said side wall insulators, forming an emitter region of said bipolar transistor in said emitter-forming region, and forming source and drain regions of said MISFET in said source- and drain-forming regions.
Claim 4
Dependent Claim
63 words
A method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the step of forming said side wall insulators include forming an insulator layer over said main surface of said semiconductor body and anisotropically etching said insulator layer, thereby to leave a part of said insulator layer on said side surfaces of said base lead-out electrode and said gate electrode.
Claim 5
Dependent Claim
31 words
A method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein said side wall insulators are formed in self-alignment to said base lead-out electrode and said gate electrode.
Claim 6
Dependent Claim
67 words
A method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the step of forming said emitter region of said bipolar transistor includes a sub-step of forming a polycrystalline silicon layer doped with third impurities of the second conductivity type over said emitter-forming region and a base lead-out region, and a sub-step of introducing said third impurities into said emitter-forming region by thermal diffusion.
Claim 7
Dependent Claim
49 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein each of said first metal silicide layer and said second metal silicide layer is made of a material selected from the group consisting of tungsten silicide, molybdenum silicide, titanium silicide, platinum silicide and tantalum silicide.
Claim 8
Dependent Claim
60 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a step of diffusing a part of said first impurities of said first conductivity type from said first silicon film part into said main surface of said semiconductor body, thereby to form an extrinsic base region, of the first conductivity type, of said bipolar transistor.
Claim 9
Dependent Claim
32 words
A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein said base lead-out electrode is patterned so as to have a tetragonal ring shape in a plane view.
Claim 10
Dependent Claim
57 words
A method of manufacturing a semiconductor integrated circuit device according to claim 8, further comprising a step of introducing fourth impurities, of the first conductivity type, into the main surface surrounded by said base lead-out electrode of the tetragonal ring shape, thereby to form an intrinsic base region, of the first conductivity type, of said bipolar transistor.
Claim 11
Dependent Claim
27 words
A method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein said intrinsic base region is formed in self-alignment to said base lead-out electrode.
Claim 12
Dependent Claim
36 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first impurities of said first conductivity type include boron, and wherein said second impurities of said second conductivity type include phosphorous.
Claim 13
Dependent Claim
28 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the silicon oxide film is formed prior to the patterning of the silicon film.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-10 | 1998-04-11 | 1998-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-10 | 2002-04-11 | 2002-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-10 | 2006-04-11 | 2006-10-11 | $7700.00 | Window Closed / Lapsed |