Data input buffer circuit for use in a semiconductor memory device

Claim 2

A data input buffer circuit in a semiconductor memory device, said data input buffer circuit comprising: a first transistor having a first gate electrode; an insulation gate field effect transistor having a channel connected between a channel of said first transistor and a reference voltage terminal for providing a reference voltage, and a conductivity of said insulation gate field effect transistor being controlled in response to a voltage level of a supply voltage terminal for providing a supply voltage; and a reference voltage generation circuit comprising a plurality of clamping circuits each generating different clamping voltages, and generating a reference voltage generation circuit signal being received by a gate of said insulation gate field effect transistor.

Claim 3

A data input buffer circuit according to claim 1, wherein a junction between said insulation gate field effect transistor and said first transistor is: charged when a voltage of said supply voltage terminal is at a first condition; and discharged to said reference voltage through the channel of said insulation gate field effect transistor when said voltage of said supply voltage terminal is at a second condition.

Claim 4

A data input buffer circuit in a semiconductor device, comprising: resistance means connected between a supply voltage terminal for providing a supply voltage and a reference node, for conducting a current; data input buffer means connected between a reference voltage terminal for providing a reference voltage and said reference node, for receiving and converting a semiconductor device input level signal into an internal level signal in response to a trip level; transistor for stabilizing a voltage of said reference node by regulating a level of said current, said transistor having a gate receiving a reference voltage signal; and a reference voltage generation circuit for generating said reference voltage signal, comprising a plurality of clamping circuits each having a different clamping voltage.

Claim 5

A data input buffer circuit in a semiconductor device, comprising: resistance means connected between a supply voltage terminal for providing a supply voltage and a reference node, for conducting a current; data input buffer means connected between a reference voltage terminal for providing a reference voltage and said reference node, for receiving and converting a semiconductor device input level signal into an internal level signal in response to a trip level; transistor for stabilizing a voltage of said reference node by regulating a level of said current, said transistor having a gate receiving a reference voltage signal; and a reference voltage generation circuit for generating said reference voltage signal, comprising a plurality of clamping circuits each having a different clamping voltage.

Claim 6

A data input buffer circuit, as claimed in claim 3, wherein said data input buffer means comprises: a P-channel transistor having a channel connected between said reference node and a data input buffer output node, and a gate electrode receiving said semiconductor device input level signal; and a N-channel transistor having a channel connected to said data input buffer output node and a gate electrode receiving said semiconductor device input level signal.

Claim 7

A data input buffer circuit in a semiconductor device, comprising: resistance means connected between a supply voltage terminal for providing a supply voltage and a reference node, for conducting a current; data input buffer means connected between a reference voltage terminal for providing a reference voltage and said reference node, for receiving and converting a semiconductor device input level signal into an internal level signal in response to a trip level; first transistor means for stabilizing a voltage of said reference node by regulating a level of said current, said transistor having a gate electrode receiving a reference voltage signal; and a reference voltage generation circuit for generating said reference voltage signal, said reference voltage generation circuit comprising: voltage follower means connected between said gate electrode of said transistor means and said supply voltage terminal; first clamping means connected between said gate electrode of said transistor means and said reference voltage terminal; and second clamping means connected between said gate electrode of said transistor means and said reference voltage terminal.

Claim 8

A data input buffer circuit in a semiconductor device, comprising: resistance means connected between a supply voltage terminal for providing a supply voltage and a reference node, for conducting a current; data input buffer means connected between a reference voltage terminal for providing a reference voltage and said reference node, for receiving and converting a semiconductor device input level signal into an internal level signal in response to a trip level; first transistor means for stabilizing a voltage of said reference node by regulating a level of said current, said transistor having a gate electrode receiving a reference voltage signal; and a reference voltage generation circuit for generating said reference voltage signal, said reference voltage generation circuit comprising: voltage follower means connected between said gate electrode of said transistor means and said supply voltage terminal; first clamping means connected between said gate electrode of said transistor means and said reference voltage terminal; and second clamping means connected between said gate electrode of said transistor means and said reference voltage terminal.

Claim 9

A data input buffer circuit, as claimed in claim 5, wherein said voltage follower means comprises a plurality of P-channel metal oxide semiconductor transistors connected in series.

Claim 10

A data input buffer circuit, as claimed in claim 5, wherein said first clamping means comprises a plurality of series connected P-channel metal oxide semiconductor transistors and an N-channel metal oxide semiconductor transistor connected in series, wherein a gate electrode of said N-channel metal oxide semiconductor transistor is connected to said supply voltage terminal.

Claim 11

A data input buffer circuit, as claimed in claim 5, wherein said second clamping means comprises a plurality of series connected N-channel MOS transistors, wherein a gate electrode of one of said plurality of N-channel MOS transistors is connected to said supply voltage terminal.

Claim 12

A data input buffer circuit, as claimed in claim 5, wherein said first clamping means comprises a plurality of series connected P-channel MOS transistors and an N-channel MOS transistor connected in series, wherein a gate electrode of said N-channel MOS transistor is connected to receive an enable signal.

Claim 13

A data input buffer circuit in a semiconductor device, comprising: an enable transistor connected between a supply voltage terminal and a source node, for enabling said data input buffer circuit in response to a buffer enable signal, said supply voltage terminal for providing a supply voltage; an input voltage receiving portion comprising a first input transistor connected between said source node and a sensing node and receiving an input voltage at a gate electrode, a second input transistor and a third input transistor cascade connected between said sensing node and a reference voltage terminal, each one of said third input transistor and said second input transistor for receiving said input voltage at a corresponding gate electrode, said reference voltage terminal for providing a reference voltage; a current regulating transistor connected between said source node and said reference voltage terminal, for regulating a current through said enable transistor in response to a reference voltage signal indicative of a voltage level of said supply voltage terminal to thereby stabilize a trip voltage of said data input buffer circuit, and a reference voltage generation circuit for generating said reference voltage signal, said reference voltage generation circuit comprising a clamping circuit for clamping said reference voltage signal to a particular level, connected between a gate electrode of said current regulating transistor and said reference voltage terminal.

Claim 14

A data input buffer circuit in a semiconductor device, comprising: an enable transistor connected between a supply voltage terminal and a source node, for enabling said data input buffer circuit in response to a buffer enable signal, said supply voltage terminal for providing a supply voltage; an input voltage receiving portion comprising a first input transistor connected between said source node and a sensing node and receiving an input voltage at a gate electrode, a second input transistor and a third input transistor cascade connected between said sensing node and a reference voltage terminal, each one of said third input transistor and said second input transistor for receiving said input voltage at a corresponding gate electrode, said reference voltage terminal for providing a reference voltage; a current regulating transistor connected between said source node and said reference voltage terminal, for regulating a current through said enable transistor in response to a reference voltage signal indicative of a voltage level of said supply voltage terminal to thereby stabilize a trip voltage of said data input buffer circuit, and a reference voltage generation circuit for generating said reference voltage signal, said reference voltage generation circuit comprising a clamping circuit for clamping said reference voltage signal to a particular level, connected between a gate electrode of said current regulating transistor and said reference voltage terminal.

Claim 15

A data input buffer circuit in a semiconductor device comprising: an enable transistor between a supply voltage terminal and a source node, for enabling said data input buffer circuit in response to a buffer enable signal, said supply voltage terminal for providing a supply voltage; an input voltage receiving portion comprising a first input transistor connected between said source node and a sensing node and receiving an input voltage at a gate electrode, a second input transistor and a third input transistor cascade connected between said sensing node and a reference voltage terminal, each one of said second input transistor and said third input transistor for receiving said input voltage at a corresponding gate electrode, said reference voltage terminal for providing a reference voltage; a current regulating transistor connected between said source node and said reference voltage terminal, for resulting a current through said enable transistor in response to a reference voltage signal indicative of a voltage level of said supply voltage terminal to thereby stabilize a trip voltage of said data input buffer circuit; and a reference voltage generation circuit for generating said reference voltage signal, said reference voltage generation circuit comprising a first clamping circuit and a second clamping circuit connected in parallel between a gate of said current regulating transistor and said reference voltage terminal.

Claim 16

A data input buffer circuit in a semiconductor device comprising: an enable transistor between a supply voltage terminal and a source node, for enabling said data input buffer circuit in response to a buffer enable signal, said supply voltage terminal for providing a supply voltage; an input voltage receiving portion comprising a first input transistor connected between said source node and a sensing node and receiving an input voltage at a gate electrode, a second input transistor and a third input transistor cascade connected between said sensing node and a reference voltage terminal, each one of said second input transistor and said third input transistor for receiving said input voltage at a corresponding gate electrode, said reference voltage terminal for providing a reference voltage; a current regulating transistor connected between said source node and said reference voltage terminal, for resulting a current through said enable transistor in response to a reference voltage signal indicative of a voltage level of said supply voltage terminal to thereby stabilize a trip voltage of said data input buffer circuit; and a reference voltage generation circuit for generating said reference voltage signal, said reference voltage generation circuit comprising a first clamping circuit and a second clamping circuit connected in parallel between a gate of said current regulating transistor and said reference voltage terminal.

Claim 17

A data input buffer as claimed in claim 11, wherein said first clamping circuit and said second clamping circuit have different clamping voltages.

Claim 18

A data input buffer as claimed in claim 11, wherein said first clamping circuit comprises an N-MOS transistor having a gate electrode connected to said supply voltage terminal and being series connected with a plurality of diode connected P-MOS transistors.

Claim 19

A data input buffer as claimed in claim 11, wherein said second clamping circuit comprises a first clamping transistor having a gate electrode connected to said supply voltage terminal and being series connected with a plurality of diode connected transistors.

Claim 20

A data input buffer as claimed in claim 11, wherein said reference voltage generation circuit further comprises a voltage follower connected between said supply voltage terminal and said gate electrode of said current regulating transistor.

Claim 21

A data input buffer as claimed in claim 15, wherein said voltage follower comprises a plurality of diode connected transistors connected in series to each other.

Claim 22

A data input buffer as claimed in claim 11, wherein said reference voltage generation circuit further comprises a voltage follower connected between said supply voltage terminal and said gate electrode of said current regulating transistor.

Claim 23

A data input buffer as claimed in claim 17, wherein said voltage follower comprises a plurality of diode connected transistors connected in series to each other.

Claim 24

A data input buffer circuit in a semiconductor device, comprising: an enable transistor connected between a supply voltage terminal and a source node, for enabling said data input buffer circuit in response to a buffer enable signal, said supply voltage terminal for providing a supply voltage; an input voltage receiving portion comprising a plurality of input transistors connected between said source node and a reference voltage terminal, each one of said input transistors coupled for receiving an input voltage at a gate electrode, said reference voltage terminal for providing a reference voltage; a current regulating transistor connected between said source node and said reference voltage terminal, for regulating a current through said enable transistor in response to a reference voltage signal indicative of a voltage level of said supply voltage terminal and thereby stabilizing a trip voltage of said data input buffer circuit; and a reference voltage generation circuit for generating said reference voltage signal, said reference voltage generation circuit comprising a first clamping circuit and a second clamping circuit connected in parallel between a gate electrode of said current regulating transistor and said reference voltage terminal.

Claim 25

A data input buffer circuit in a semiconductor device, comprising: an enable transistor connected between a supply voltage terminal and a source node, for enabling said data input buffer circuit in response to a buffer enable signal, said supply voltage terminal for providing a supply voltage; an input voltage receiving portion comprising a plurality of input transistors connected between said source node and a reference voltage terminal, each one of said input transistors coupled for receiving an input voltage at a gate electrode, said reference voltage terminal for providing a reference voltage; a current regulating transistor connected between said source node and said reference voltage terminal, for regulating a current through said enable transistor in response to a reference voltage signal indicative of a voltage level of said supply voltage terminal and thereby stabilizing a trip voltage of said data input buffer circuit; and a reference voltage generation circuit for generating said reference voltage signal, said reference voltage generation circuit comprising a first clamping circuit and a second clamping circuit connected in parallel between a gate electrode of said current regulating transistor and said reference voltage terminal.

Claim 26

A data input buffer as claimed in claim 19, wherein said first clamping circuit and said second clamping circuit have different clamping voltages.

Claim 27

A data input buffer as claimed in claim 19, wherein said first clamping circuit comprises an N-MOS transistor having a gate electrode connected to said supply voltage terminal and being series connected with a plurality of diode connected P-MOS transistors.

Claim 28

A data input buffer as claimed in claim 19, wherein said second clamping circuit comprises a first clamping transistor having a gate electrode connected to said supply voltage terminal and being series connected with a plurality of diode connected transistors.

Claim 29

A data input buffer as claimed in claim 19, wherein said reference voltage generation circuit further comprises a voltage follower connected between said supply voltage terminal and said gate electrode of said current regulating transistor.

Claim 30

A data input buffer as claimed in claim 23, wherein said voltage follower comprises a plurality of diode connected transistors connected in series.

Claim 31

The data input buffer as claimed in claim 1, further comprising an input voltage receiving portion, said input voltage receiving portion comprising: a second transistor connected between a source node and a sensing node and receiving an input voltage at a second gate electrode; a third transistor connected between said sensing node and said reference voltage terminal and receiving said input voltage at a third gate electrode; a fourth transistor cascade connected between said third transistor and said reference voltage terminal and receiving said input voltage at a fourth gate electrode.

Claim 32

The data input buffer as claimed in claim 1, wherein said reference voltage generation circuit further comprises voltage follower means comprising a plurality of P-channel metal oxide semiconductor transistors connected in series.

Claim 33

The data input buffer as claimed in claim 3, wherein said reference voltage generation circuit further comprises voltage follower means comprising a plurality of P-channel metal oxide semiconductor transistors connected in series.

Claim 34

The data input buffer as claimed in claim 10, wherein said clamping circuit comprises first and second clamping means, said first and second clamping means having different clamping voltages.

Claim 35

The data input buffer as claimed in claim 10, wherein said reference voltage generation circuit further comprises voltage follower means comprising a plurality of P-channel metal oxide semiconductor transistors connected in series.