Method for reverse programming of a flash EEPROM

Claim 1

A method of erasing, programming, and verifying flash electrically erasable programmable read-only memory cells, each cell having a source, drain, control gate, floating gate, and substrate; the method comprising: a. applying a positive high voltage to each cell control gate while grounding or floating the drain, thereby erasing a cell data bit and providing a high threshold voltage V t on each cell; b. programming each cell by applying a negative second voltage to each cell control gate while grounding the source and applying a voltage V CC to the drain to program a "one" or grounding the drain to program a "zero", thereby providing a lower V t on each "one" cell; c. verifying the programming and threshold voltage of each cell by a read verification cycle, said read cycle further comprising: i. applying voltage V CC to a selected cell gate and grounding unselected cell gates; ii. applying a positive voltage to a selected cell drain and floating an unselected cell drain; and then d. repeating the programming and read verification cycle only on selected cells having a threshold voltage V t above a preferred threshold voltage distribution curve, until all cells have a V t that lie below the preferred voltage distribution curve.

Claim 2

A method of erasing, programming, and verifying flash electrically erasable programmable read-only memory cells, each cell having a source, drain, control gate, floating gate, and substrate; the method comprising: a. applying a positive high voltage to each cell control gate while grounding or floating the drain, thereby erasing a cell data bit and providing a high threshold voltage V t on each cell; b. programming each cell by applying a negative second voltage to each cell control gate while grounding the source and applying a voltage V CC to the drain to program a "one" or grounding the drain to program a "zero", thereby providing a lower V t on each "one" cell; c. verifying the programming and threshold voltage of each cell by a read verification cycle, said read cycle further comprising: i. applying voltage V CC to a selected cell gate and grounding unselected cell gates; ii. applying a positive voltage to a selected cell drain and floating an unselected cell drain; and then d. repeating the programming and read verification cycle only on selected cells having a threshold voltage V t above a preferred threshold voltage distribution curve, until all cells have a V t that lie below the preferred voltage distribution curve.

Claim 4

A method of erasing, selectively programming, and verifying a flash electrically erasable read-only memory (EEPROM) cell within an array of flash EEPROM cells arranged in rows and columns, each cell in a row having a control gate connecting a wordline and each cell in a column having a drain connection to a bitline; the method comprising: a. erasing the cell array by simultaneous application of a high positive voltage on the wordlines and having a float or zero volts on the bit lines and a grounded source, thereby providing a high threshold voltage V t on all cells; b. programming a selected cell or cells by application of a negative voltage on a selected wordline and application of a zero or a positive voltage on a selected bitline, thereby providing a lower threshold voltage V t on selected cells; c. verifying a proper data input and lower voltage V t on selected cells by application of a lower positive voltage on the selected wordline and application of a low, positive voltage on the selected bitline and floating unselected bitlines; and d. repeating the programming and verifying steps above until all cell threshold voltages V t lie within a preferred tight, normal, distribution curve.

Claim 5

A method of erasing, selectively programming, and verifying a flash electrically erasable read-only memory (EEPROM) cell within an array of flash EEPROM cells arranged in rows and columns, each cell in a row having a control gate connecting a wordline and each cell in a column having a drain connection to a bitline; the method comprising: a. erasing the cell array by simultaneous application of a high positive voltage on the wordlines and having a float or zero volts on the bit lines and a grounded source, thereby providing a high threshold voltage V t on all cells; b. programming a selected cell or cells by application of a negative voltage on a selected wordline and application of a zero or a positive voltage on a selected bitline, thereby providing a lower threshold voltage V t on selected cells; c. verifying a proper data input and lower voltage V t on selected cells by application of a lower positive voltage on the selected wordline and application of a low, positive voltage on the selected bitline and floating unselected bitlines; and d. repeating the programming and verifying steps above until all cell threshold voltages V t lie within a preferred tight, normal, distribution curve.

Claim 10

A method of erasing, selectively programming, and verifying a flash electrically erasable read-only memory (EEPROM) cell within an array of flash EEPROM cells arranged in rows and columns, each cell in a row having a control gate connecting a wordline and each cell in a column having a drain connection to a bitline; the method comprising: a. erasing the cell array by simultaneous application of about +17 volts on the wordlines and having a float or zero volts on the bit lines, thereby providing a high threshold voltage V t on all cells; b. programming a selected cell or cells by application of -10 volts on a selected wordline and application of a zero or a positive voltage on a selected bitline and a grounded source, thereby providing a lower threshold voltage V t on selected cells; c. verifying a proper data input and lower voltage V t on selected cells by application of about +5 volts on the selected wordline and application of +1.5 volts on the selected bitline and floating unselected bitlines; and d. repeating the programming and verifying steps above until all cell threshold voltages V t lie within a preferred tight, normal, distribution curve above zero volts and below +5 volts.

Claim 11

A method of erasing, selectively programming, and verifying a flash electrically erasable read-only memory (EEPROM) cell within an array of flash EEPROM cells arranged in rows and columns, each cell in a row having a control gate connecting a wordline and each cell in a column having a drain connection to a bitline; the method comprising: a. erasing the cell array by simultaneous application of about +17 volts on the wordlines and having a float or zero volts on the bit lines, thereby providing a high threshold voltage V t on all cells; b. programming a selected cell or cells by application of -10 volts on a selected wordline and application of a zero or a positive voltage on a selected bitline and a grounded source, thereby providing a lower threshold voltage V t on selected cells; c. verifying a proper data input and lower voltage V t on selected cells by application of about +5 volts on the selected wordline and application of +1.5 volts on the selected bitline and floating unselected bitlines; and d. repeating the programming and verifying steps above until all cell threshold voltages V t lie within a preferred tight, normal, distribution curve above zero volts and below +5 volts.