Method for debugging in a parallel computer system and system for the same

Claim 2

In a parallel computer system including a main processor and a plurality of processors each having an identifier, a method for sequentially executing parallel programs for identification of bugs comprising the steps of: (a) registering, by the main processor, data sets for said plurality of processors into a queue in a predetermined order, each data set including an identifier of one of the processors and an execution address of one of the programs corresponding to the processor; (b) removing, by the main processor, one of the data sets registered in said queue; (c) controlling, by the main processor, said processor identified by the identifier included in the removed data set to execute the corresponding one program until said processor has fallen into either an end state or a waiting state for either data to be supplied from another processor or synchronization with another processor, while inhibiting operation of the other processors; (d) registering in said queue by the main processor, a data set including the identifier of the executing processor and an address from which the execution is restarted when the executing processor has fallen into the waiting state; and (e) repeating said steps (b) to (d) until a predetermined end condition is satisfied.

Claim 3

The method according to claim 1, wherein said step (e) includes the steps of: determining that the end condition is satisfied, when the data sets registered in said queue are the same before and after a repetition of said steps (b) to (d); executing said steps (b) to (d) again; and stopping further repetition of said step (b) to (d) when said data sets are determined to be same.

Claim 4

The method according to claim 2, further comprising the step of outputting the data sets registered in said queue when the further repetition of said steps (b) to (d) is stopped.

Claim 5

The method according to claim 1, wherein said predetermined order is arbitrarily determined.

Claim 6

The method according to claim 1, wherein said predetermined order is determined based upon the number of data transmissions executed in each program.

Claim 7

The method according to claim 1, wherein said predetermined order is determined by generating random numbers based on an execution time of each program.

Claim 8

The method according to claim 1, further comprising the step of linking a debug routine with the user program without compiling the user program again, said steps (a) to (e) being based on the debug routine.

Claim 9

The method according to claim 1, wherein each program includes a statement for outputting a variable array and a referred or defined area of the variable array for each access to the variable array, said method further comprising executing steps (a) to (e) in different order.

Claim 10

In a parallel computer system including a main processor and a plurality of processors each having an identifier, a method for debugging a plurality of parallel programs of a user program, each parallel program including code for outputting a variable array, an accessed part thereof and definition or reference of the part by sequentially executing the parallel programs for identification of bugs, said method being executed by the computer system and comprising the steps of: (a) allocating the parallel programs to said processors, respectively; (b) registering the identifiers of said plurality of processors in a table in accordance with a predetermined rule; (c) controlling said processors to execute the allocated parallel programs in an order of numbers such that only one processor is active at a time, until each processor is brought into one of an end state and a waiting state for either data or synchronization, while outputting trace data; (d) registering the identifier of the processor brought into the waiting state in the table; (e) repeating said steps (c) and (d) until an end condition is satisfied; and (f) repeating said steps (b) to (e), wherein said step (b) is executed such that serial numbers are assigned to the processors in a different order.

Claim 11

In a parallel computer system including a main processor and a plurality of processors each having an identifier, a method for debugging a plurality of parallel programs of a user program, each parallel program including code for outputting a variable array, an accessed part thereof and definition or reference of the part by sequentially executing the parallel programs for identification of bugs, said method being executed by the computer system and comprising the steps of: (a) allocating the parallel programs to said processors, respectively; (b) registering the identifiers of said plurality of processors in a table in accordance with a predetermined rule; (c) controlling said processors to execute the allocated parallel programs in an order of numbers such that only one processor is active at a time, until each processor is brought into one of an end state and a waiting state for either data or synchronization, while outputting trace data; (d) registering the identifier of the processor brought into the waiting state in the table; (e) repeating said steps (c) and (d) until an end condition is satisfied; and (f) repeating said steps (b) to (e), wherein said step (b) is executed such that serial numbers are assigned to the processors in a different order.

Claim 12

The method according to claim 9, wherein the end condition is that the registered identifiers are the same as those before the repeating of said step (e).

Claim 13

The method according to claim 9, wherein said step (e) further comprises the step of outputting the identifiers of the processors in the waiting state when the end condition is satisfied.

Claim 14

In a multiprocessor system including a plurality of processors each having an identifier, a method for debugging a plurality of parallel programs of a user program by sequentially executing the parallel programs to identify a bug, said method being executed by the multiprocessor system and comprising the steps of: (a) allocating the parallel programs to said processors, respectively; (b) registering data sets for said processors in a execution waiting table in a predetermined order, each data set including an identifier of one of the processors and an address to be run therefrom of a corresponding parallel program allocated to said one processor; (c) referring to one of the data sets registered in the execution waiting table in accordance with the predetermined order to control one of the processors for the referred data set to execute the parallel program allocated to said one processor from said address within the referred data set while updating said address until the processor is brought into either an end state or a waiting state for either data or synchronization; and (d) registering a data set for the processor in the execution waiting table when the processor has been brought into the waiting state, to repeat said step (c) until a predetermined end condition is satisfied.

Claim 15

In a multiprocessor system including a plurality of processors each having an identifier, a method for debugging a plurality of parallel programs of a user program by sequentially executing the parallel programs to identify a bug, said method being executed by the multiprocessor system and comprising the steps of: (a) allocating the parallel programs to said processors, respectively; (b) registering data sets for said processors in a execution waiting table in a predetermined order, each data set including an identifier of one of the processors and an address to be run therefrom of a corresponding parallel program allocated to said one processor; (c) referring to one of the data sets registered in the execution waiting table in accordance with the predetermined order to control one of the processors for the referred data set to execute the parallel program allocated to said one processor from said address within the referred data set while updating said address until the processor is brought into either an end state or a waiting state for either data or synchronization; and (d) registering a data set for the processor in the execution waiting table when the processor has been brought into the waiting state, to repeat said step (c) until a predetermined end condition is satisfied.

Claim 16

The method according to claim 12, further comprising (e) repeating said steps (b) to (d) when the end condition is satisfied, wherein said step (b) is executed in a different order.

Claim 17

The method according to claim 13, wherein said step (d) includes the step of determining that the end condition is satisfied when no change is made in a content of the execution waiting table before and after the plurality of parallel programs are executed.

Claim 18

The method according to claim 13, wherein each parallel program include code outputting a name of a variable array, an accessed part thereof and definition or reference of the part as trace data, the array being shared by some of the parallel programs, and said step (c) further comprising the step of outputting the traced data for each access to the array during the execution of the allocated parallel programs.

Claim 19

A parallel computer system comprising: a plurality of processors, each processor being assigned with an identifier and executing parallel programs of a user program; an execution waiting queue; means for registering data sets for said plurality of processors into said execution waiting queue in a predetermined order, each data set including an identifier of one of the processors and an execution start address of one of the parallel programs to be executed by the one processor; means for causing said processors in accordance with the registered data sets, to execute the user program such that only one processor executes the corresponding parallel program one at a time in the order until the processor is brought into one of an end state and a waiting state for either data or synchronization; means for registering a data set for the processor brought into the waiting state in said queue again; and measn for stopping the control when a predetermined end condition is satisified, to detect bugs in the parallel programs.

Claim 20

A parallel computer system comprising: a plurality of processors, each processor being assigned with an identifier and executing parallel programs of a user program; an execution waiting queue; means for registering data sets for said plurality of processors into said execution waiting queue in a predetermined order, each data set including an identifier of one of the processors and an execution start address of one of the parallel programs to be executed by the one processor; means for causing said processors in accordance with the registered data sets, to execute the user program such that only one processor executes the corresponding parallel program one at a time in the order until the processor is brought into one of an end state and a waiting state for either data or synchronization; means for registering a data set for the processor brought into the waiting state in said queue again; and measn for stopping the control when a predetermined end condition is satisified, to detect bugs in the parallel programs.