Fault analysis apparatus for memories having redundancy circuits

Claim 1

An apparatus for analyzing faults in a memory having a redundancy circuit, comprising: an algorithmic pattern generator for generating address signals to select memory cells in a memory under test MUT), said MUT being a measurement object having a redundancy circuit, said algorithmic pattern generator generating data supplied to said selected memory cells; comparison means for performing a read operation of said data after data have been written into said selected memory cells selected by said address signals and comparing data read with said data supplied from said algorithmic pattern generator to determine whether or not both said data read and said data from said algorithmic pattern generator are in agreement, if both said data read and said data from said algorithmic pattern generator are not in agreement, generating a fault signal to indicate that said selected memory cells are faulty; a fault analysis memory having a first function of storing fault data from a plural number of memory cells of said MUT in one memory cell in said fault analysis memory ,and a second function of storing said fault data from one of said memory cells of said MUT in said one memory cell of said fault analysis memory; and address allocation means for receiving address signals from said algorithmic pattern generator and performing address allocation for said fault analysis memory so that said plural number of memory cells of said memory under test correspond, based on a predetermined rule, to a single memory cell of said fault analysis memory, and wherein said fault analysis memory writes fault information into a memory cell corresponding to a memory cell of said MUT having the fault, whenever said fault signal indicating said fault is sent from said comparison means.

Claim 2

An apparatus for analyzing faults in a memory having a redundancy circuit, comprising: an algorithmic pattern generator for generating address signals to select memory cells in a memory under test MUT), said MUT being a measurement object having a redundancy circuit, said algorithmic pattern generator generating data supplied to said selected memory cells; comparison means for performing a read operation of said data after data have been written into said selected memory cells selected by said address signals and comparing data read with said data supplied from said algorithmic pattern generator to determine whether or not both said data read and said data from said algorithmic pattern generator are in agreement, if both said data read and said data from said algorithmic pattern generator are not in agreement, generating a fault signal to indicate that said selected memory cells are faulty; a fault analysis memory having a first function of storing fault data from a plural number of memory cells of said MUT in one memory cell in said fault analysis memory ,and a second function of storing said fault data from one of said memory cells of said MUT in said one memory cell of said fault analysis memory; and address allocation means for receiving address signals from said algorithmic pattern generator and performing address allocation for said fault analysis memory so that said plural number of memory cells of said memory under test correspond, based on a predetermined rule, to a single memory cell of said fault analysis memory, and wherein said fault analysis memory writes fault information into a memory cell corresponding to a memory cell of said MUT having the fault, whenever said fault signal indicating said fault is sent from said comparison means.