US5366931A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fabrication method for on-chip decoupling capacitor
Assignee: SK Hynix Inc
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Filing: 1992-10-28
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Granted: 1994-11-22
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Expires: 2012-10-28
Abstract
Abstract This invention relates to a technology designed to fabricate the on-chip decoupling capacitor wherein both semiconductor chip and lead-frame are used as each electrode of capacitor and the source voltage is applied to the electrode, thus maximizing the capacity of decoupling capacitor.
Inventors
- 👤 Hong S. Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 00:44
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10W; H10W70/00; H10W70/40; H10W70/475; H10W44/00; H10W44/601
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
84 words
A method for fabricating a decoupling capacitor in semiconductor IC, comprising the steps of: using a back side of the semiconductor chip as one electrode of the decoupling capacitor, which is designed to enlarge the capacitor area; and using a lead-frame as the remaining electrode of the decoupling capacitor, said lead-frame being so constructed as to package the semiconductor chip, wherein the voltage is applied between the semiconductor chip and lead-frame, and said chip and lead-frame are used as each electrode of the capacitor.
Claim 2
Independent Claim
84 words
A method for fabricating a decoupling capacitor in semiconductor IC, comprising the steps of: using a back side of the semiconductor chip as one electrode of the decoupling capacitor, which is designed to enlarge the capacitor area; and using a lead-frame as the remaining electrode of the decoupling capacitor, said lead-frame being so constructed as to package the semiconductor chip, wherein the voltage is applied between the semiconductor chip and lead-frame, and said chip and lead-frame are used as each electrode of the capacitor.
Claim 3
Dependent Claim
17 words
The method of claim 1, wherein a dielectric is inserted between the semiconductor chip and the lead-frame.
Claim 4
Dependent Claim
29 words
The method of claim 1, wherein an N-type plate is used as the semiconductor chip and is biased with positive voltage and the lead-frame is in a grounded state.
Claim 5
Dependent Claim
23 words
The method of claim 1, wherein the lead-frame is biased with a positive voltage and the semiconductor chip is in a grounded state.
Claim 6
Dependent Claim
35 words
The method of claim 4, wherein the semiconductor chip is biased with a negative back biased voltage and the lead-frame is biased with a voltage from the set consisting of positive voltage or grounded voltage.
References Cited (Backward Citations)
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US5179039A
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US5032892A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-21 | 1998-05-23 | 1998-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-21 | 2002-05-23 | 2002-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-21 | 2006-05-23 | 2006-11-22 | $7700.00 | Window Closed / Lapsed |