Method and system for routing cells in an ATM switch

Claim 2

A switch for routing information cells having destination addresses from input ports of the switch to output ports of the switch on a cell-by-cell basis, the switch comprising: a plurality of input buffers having outputs for storing the information cells, the input buffers being arranged in one or more groups; a central switch fabric including a plurality of crosspoint switch switching planes having inputs and outputs, each of said switching planes having a constant signal delay that is the same for all of the switching planes, a path switch associated with each group of input buffers for selectively connecting the signals appearing on the outputs of the buffers of that group to the inputs of the plurality of switching planes; a plurality of contention resolution devices (CRD), one CRD being associated with each of said switching planes for resolving contention among the information cells for access to the outputs of said switching plane on the cell-by-cell basis, each CRD providing indication signals for winning and losing information cells; a feedback path means for communicating win/lose signals from the CRDs back to the plurality of input buffers from which the winning and losing information cells originated, said feedback path means maintaining routing correspondence between input buffers and switching planes for both the signals traveling in a forward direction and the associated win/lose contention signals traveling in a reverse direction; and an output buffered switch including a plurality of output buffers arranged in one or more groups for receiving the information cells from the outputs of the plurality of switching planes for routing the information cells to the proper output port of the switch in accordance with destination addresses of the information cells.

Claim 3

The switch as claimed in claim 1 further comprising path controller logic means for asserting routing priority for information cells and wherein the path switch is a crosspoint switch controlled by the path controller logic means.

Claim 8

A switch for routing information cells having destination addresses from input ports of the switch to output ports of the switch, the switch comprising: a plurality of input buffers having outputs for storing the information cells, the input buffers being arranged in one or more groups; a central switch fabric including a plurality of switching planes having inputs and outputs; a path switch associated with each group of input buffers for selectively connecting the signals appearing on the outputs of the buffers of that group to the inputs of the plurality of switching planes; a plurality of contention resolution devices (CRD), one CRD being associated with each of said switching planes for resolving contention among information cells for access to the outputs of said switching plane, each CRD providing indication signals for winning and losing information cells; a feedback path means for communicating win/lose signals from the CRDs back to the plurality of input buffers from which the winning and losing information cells originated; and an output buffered switch including a plurality of output buffers arranged in one or more groups for receiving the information cells from the outputs of the plurality of switching planes for routing the information cells to the proper output port of the switch in accordance with destination addresses of the information cells; and wherein the switch further comprises path controller logic means for asserting routing priority for information cells and wherein the path switch is a crosspoint switch controlled by the path controller logic means.

Claim 9

A switch for routing information cells having destination addresses from input ports of the switch to output ports of the switch, the switch comprising: a plurality of input buffers having outputs for storing the information cells, the input buffers being arranged in one or more groups; a central switch fabric including a plurality of switching planes having inputs and outputs; a path switch associated with each group of input buffers for selectively connecting the signals appearing on the outputs of the buffers of that group to the inputs of the plurality of switching planes; a plurality of contention resolution devices (CRD), one CRD being associated with each of said switching planes for resolving contention among information cells for access to the outputs of said switching plane, each CRD providing indication signals for winning and losing information cells; a feedback path means for communicating win/lose signals from the CRDs back to the plurality of input buffers from which the winning and losing information cells originated; and an output buffered switch including a plurality of output buffers arranged in one or more groups for receiving the information cells from the outputs of the plurality of switching planes for routing the information cells to the proper output port of the switch in accordance with destination addresses of the information cells; and wherein the switch further comprises path controller logic means for asserting routing priority for information cells and wherein the path switch is a crosspoint switch controlled by the path controller logic means.

Claim 10

A switch for routing information cells having destination addresses from input ports of the switch to output ports of the switch, the switch comprising: a plurality of input buffers having outputs for storing the information cells, the input buffers being arranged in one or more groups; a central switch fabric including a plurality of switching planes having inputs and outputs; a path switch associated with each group of input buffers for selectively connecting the signals appearing on the outputs of the buffers of that group to the inputs of the plurality of switching planes; a plurality of contention resolution devices (CRD), one CRD being associated with each of said switching planes for resolving contention among information cells for access to the outputs of said switching plane, each CRD providing indication signals for winning and losing information cells; a feedback path means for communicating win/lose signals from the CRDs back to the plurality of input buffers from which the winning and losing information cells originated; and an output buffered switch including a plurality of output buffers arranged in one or more groups for receiving the information cells from the outputs of the plurality of switching planes for routing the information cells to the proper output port of the switch in accordance with destination addresses of the information cells; and wherein the switch further comprises means for preventing output buffer overflow, said means for preventing collecting addresses of the most occupied output buffers, feeding the addresses back to the input buffers, performing address comparisons, and, inhibiting operation of said input buffers having head-of-line information cells destined for said most occupied output buffers, said means for preventing being inoperative with respect to any input buffers in danger of overflow.

Claim 11

A switch for routing information cells having destination addresses from input ports of the switch to output ports of the switch, the switch comprising: a plurality of input buffers having outputs for storing the information cells, the input buffers being arranged in one or more groups; a central switch fabric including a plurality of switching planes having inputs and outputs; a path switch associated with each group of input buffers for selectively connecting the signals appearing on the outputs of the buffers of that group to the inputs of the plurality of switching planes; a plurality of contention resolution devices (CRD), one CRD being associated with each of said switching planes for resolving contention among information cells for access to the outputs of said switching plane, each CRD providing indication signals for winning and losing information cells; a feedback path means for communicating win/lose signals from the CRDs back to the plurality of input buffers from which the winning and losing information cells originated; and an output buffered switch including a plurality of output buffers arranged in one or more groups for receiving the information cells from the outputs of the plurality of switching planes for routing the information cells to the proper output port of the switch in accordance with destination addresses of the information cells; and wherein the switch further comprises means for preventing output buffer overflow, said means for preventing collecting addresses of the most occupied output buffers, feeding the addresses back to the input buffers, performing address comparisons, and, inhibiting operation of said input buffers having head-of-line information cells destined for said most occupied output buffers, said means for preventing being inoperative with respect to any input buffers in danger of overflow.

Claim 16

A switch for routing information cells having destination addresses from input ports of the switch to output ports of the switch on a cell-by-cell basis, the switch comprising: a plurality of input buffers having outputs for storing the information cells, the input buffers being arranged in one or more groups; a central switch fabric including a plurality of switching planes having inputs and outputs; a path switch associated with each group of input buffers for selectively connecting the signal appearing on the outputs of the buffers of that group to the inputs of the plurality of switching planes; interconnecting means for interconnecting the path switches and the switching planes so that different signal paths selectable by the path switch are characterized by different sets of signals in contention for outputs of the switching planes; a plurality of contention resolution devices, one device being associated with each of said switching planes for resolving contention among information cells for access to the outputs of said switching plane on the cell-by-cell basis, each contention resolution device providing indication signals for winning and losing information cells; a feedback path means for communicating win/lose signals from the contention resolution devices back to the plurality of input buffers from which the winning and losing information cells originated; and an output buffered switch including a plurality of output buffers arranged in one or more groups for receiving the information cells from the outputs of the plurality of switching planes for routing the information cells to the proper output port of the switch in accordance with destination addresses of the information cells; and wherein each signal path selectable by a path switch traverses the central switching fabric through a different switching plane.

Claim 17

A switch for routing information cells having destination addresses from input ports of the switch to output ports of the switch on a cell-by-cell basis, the switch comprising: a plurality of input buffers having outputs for storing the information cells, the input buffers being arranged in one or more groups; a central switch fabric including a plurality of switching planes having inputs and outputs; a path switch associated with each group of input buffers for selectively connecting the signal appearing on the outputs of the buffers of that group to the inputs of the plurality of switching planes; interconnecting means for interconnecting the path switches and the switching planes so that different signal paths selectable by the path switch are characterized by different sets of signals in contention for outputs of the switching planes; a plurality of contention resolution devices, one device being associated with each of said switching planes for resolving contention among information cells for access to the outputs of said switching plane on the cell-by-cell basis, each contention resolution device providing indication signals for winning and losing information cells; a feedback path means for communicating win/lose signals from the contention resolution devices back to the plurality of input buffers from which the winning and losing information cells originated; and an output buffered switch including a plurality of output buffers arranged in one or more groups for receiving the information cells from the outputs of the plurality of switching planes for routing the information cells to the proper output port of the switch in accordance with destination addresses of the information cells; and wherein each signal path selectable by a path switch traverses the central switching fabric through a different switching plane.

Claim 18

The method as claimed in claim 7 wherein the step of assigning is controlled so that the paths of the stored cells from the input queues to the switching planes are scrambled.

Claim 19

The method as claimed in claim 3 wherein the cells have a cell period and wherein the step of assigning is performed at substantially each cell period so that the paths are scrambled on each cell period.

Claim 20

The method as claimed in claim 7 wherein the step of assigning is controlled in an adaptive fashion wherein the step of assigning is based on the cell occupancies of the input queues.

Claim 21

The method as claimed in claim 7 wherein each of the cells has a switch routing tag and wherein the method further comprises the step of routing the cells to the input queues based on the switch routing tags of the cells.

Claim 22

The method as claimed in claim 13 wherein the step of routing is based on the cell occupancies of the input queues.

Claim 23

The system as claimed in claim 8 wherein the means for assigning controls the assignment of the paths of the stored cells from the input queues to the switching planes in a scrambled fashion.

Claim 24

The system as claimed in claim 4 wherein the cells have a cell period and wherein the alignment of the paths is performed at substantially each cell period so that the paths are scrambled on each cell period.

Claim 25

The system as claimed in claim 8 wherein the means for assigning controls the assignment of the paths of the stored cells from the input queues to the switching planes in an adaptive fashion so that the assignment of the paths is based on the cell occupancies of the input queues.

Claim 26

The system as claimed in claim 8 wherein each of the cells has a switch routing tag and wherein the system further comprises means for routing the cells to the input queues based on the switch routing tags of the cells.

Claim 27

The system as claimed in claim 18 wherein the means for routing routes the cells based on the cell occupancies of the input queues.

Claim 28

The switch as claimed in claim 5 further comprising interconnecting means for interconnecting the path switches and the switching planes so that the signals on the output of any input buffer in a group can be connected to an input of any one of a plurality of different switching planes.

Claim 29

The switch as claimed in claim 5 wherein the feedback path means for communicating win/lose signals to the input buffers is a crosspoint switch controlled by the path controller logic means so as to maintain routing correspondence between input buffers and switching planes for both the signals traveling in a forward direction and the associated win/lose contention signals traveling in a reverse direction.

Claim 30

The switch as claimed in claim 5 further comprising interconnecting means for interconnecting the path switches and the switching planes so that different signal paths selectable by the path switch are characterized by different sets of signals in contention for outputs of the switching planes.

Claim 31

The switch as claimed in claim 5 wherein the one CRD associated with each of said switching planes of the central switching fabric is characterized by a known fixed preference for certain contending information cells as a function of which inputs of the switching plane and its associated CRD the contending information cells appear; and wherein each path switch is interconnected to a plurality of switching planes such that the group of input buffers attached to each path switch has available a plurality of paths and a plurality of contention priorities; and wherein the path controller logic means includes logic means to assure that any given input buffer is assigned to a path with adequate contention priority so as to avoid input buffer overflow.

Claim 32

The switch as claimed in claim 23 wherein the path controller logic means asserts routing priority for certain identified information cells so as to achieve desired enhanced switching performance for the identified information cells, such as further reduced cell loss probability, reduced cell delay, reduced cell jitter, and the like, as a function of the known fixed preference and the information cell occupancies of the input buffers.

Claim 33

The switch as claimed in claim 5 further comprising means for preventing overflow of one of the output buffers, said means for preventing providing a feedback signal to the plurality of CRDs to control the flow of information cells to the one of said output buffers or the group of output buffers of which said one is a member.