Fault tolerant hard disk array controller

Claim 2

A fault tolerant memory array control system for controlling data accesses to and from a host system bus and a memory array of discrete bulk memory units, organized by channel index and rank index, wherein bulk memory units with the same rank index are of a similar type and capacity, and bulk memory units with the same channel index share a common channel data bus, the memory array control system comprising: (a) a controller system bus for control and data communication between elements of the memory array control system; (b) a microprocessor controller coupled to the controller system bus for performing logical control of the memory array control system elements, the microprocessor controller comprising: (i) a microprocessor for executing operating control programs and configuration control programs comprising: (aa) a translation program for optimally translating address data of a host logical data access request to the memory array into a minimal set of memory array physical address and length data for accessing appropriate bulk memory units; (bb) a scheduling program for determining and executing an optimal sequence of steps by which to execute a queued set of memory array access requests by optimizing a prescribed performance function criterion; (cc) a crippled operation program for using module redundancy and parity data encoding methods for sustaining system operation after a bulk memory failure; and (dd) a computer kernel control means for coordinating all system functions and resources; and (ii) an interrupt controller connected to the microprocessor for accepting and prioritizing externally generated interrupt requests from the host system bus interface and from a drive channel controller; (c) a host computer system bus interface coupled to the controller bus; (d) a set of more than one drive channel controller, each controller of the set for coupling to a unique common channel data bus for selecting a bulk memory unit, and for control of and data transfers to and from the selected bulk memory unit sharing the common channel data bus; (e) a data path unit comprising; (i) a data path selector, having an output and more than one input, each input connected to one of the set of drive channel controllers for selecting a drive channel; and (ii) a data path coupled to the host system bus interface and connected to the data path selector output for coupling the selected drive channel to the host computer system bus.

Claim 3

A fault tolerant memory array control system as in claim 1 further comprising a data configuration program implementing a method for partitioning data amongst the bulk memory units in the memory array so that the configured RAID format is selected based on an intended application.

Claim 4

The system of claim 2 wherein the data configuration program method for partitioning data accommodates arbitrary memory array dimensions.

Claim 5

The system of claim 2, wherein the data configuration program method for partitioning data accommodates software partitioning of said memory array into multiple subarrays along physical or logical boundaries, where each subarray may be configured with a different RAID format.

Claim 6

The system of claim 1 wherein the scheduling program optimization method minimizes the performance function for finding an optimum schedule by using simplex linear programming methods.

Claim 7

The system of claim 1 wherein the scheduling program controls means for guaranteeing that the controlled response of the memory array to any particular host computer access request is not delayed indefinitely.

Claim 8

The system of claim 1 wherein the scheduling program controls means for servicing of host input and output data transfer request combinations by use of parallel access to the bulk memory units that optimize the prescribed performance function criterion.

Claim 9

The system of claim 6 wherein the scheduling program controls scheduling means for determining a sequence for executing a queued set of m host access requests to the memory array, the queued set numbers indexed 1, 2, . . . , m, the scheduling means comprising means for: (a) prescribing a performance function, D, representative of the latency for all possible sequential orders of accessing the queued set of m host access requests to the memory array, where ##EQU14## n 0 +N 0 is an initial address corresponding to a last address used to access memory, n i is a memory array address to the i th queued memory array access request, N i is a memory array block size of the i th queued memory array access request, and x i ,j is a binary valued coefficient, {0,1}, which indicates, when x i ,j =1, that an i th queued memory access is followed by a j th queued memory access; (b) minimizing the performance function, D, subject to a set of conditions as follows: ##EQU15## (c) ordering the set of m coefficients, {X ij } corresponding to X ij =1, obtained by the means for minimizing the performance function, beginning with x 0b .sbsb.1, and proceeding to the right as follows: X.sub.0b.sbsb.1 X.sub.b.sbsb.1.spsb.b.sbsb.2 X.sub.b.sbsb.2.spsb.b.sbsb.3 . . . x.sub.b.sbsb.m-1.spsb.b.sbsb.m so that a j th index of a coefficient becomes an i th index of a next right adjacent coefficient; and (d) arranging the order of the b-subscript of the m coefficients in ascending order, b 1 b 2 b 3 . . . b m , for indicating the left to right sequence for ordering the m queued access requests indexed 1, 2, . . . , m, so that, by following the order of subscripts, an optimized sequence for accessing the memory array yields an access sequence with minimum latency.

Claim 10

The system of claim 8 wherein the means for minimizing the performance function uses linear programming simplex methods.

Claim 11

The system as in claim 6 wherein the scheduling program controls scheduling means for determining an ordered sequence for executing a queued set of m host system access requests to the memory array, indexed 1, 2, . . . , m, the sequence ensuring a bounded latency for all queued host system access requests by maintaining a count of the number of times a particular access request has been rescheduled without execution, the scheduling means comprises means for: (a) prescribing a performance function, D, representative of the latency for all possible sequential orders of accessing the queued set of m host system access requests to the memory array, where ##EQU16## n 0 +N 0 is an initial address corresponding to a last array physical address used to access memory, n i is a memory array physical address to the i th queued memory access address, N i is a parameter indicating the number of blocks to be accessed beginning at address n i , X i ,j is a binary valued coefficient, {0,1}, which indicates, when x ij =1, that a i th queued memory access is followed by a j th queued memory access, and 2 -dj is a binary parameter scaling factor in which d j is a count of the number of times the j th access request has been rescheduled without execution; (b) minimizing the performance function, D, subject to a set of conditions as follows: ##EQU17## (c) ordering the set of m coefficients, {x ij }, obtained by the means for minimizing the performance function, beginning with x 0b .sbsb.1 and proceeding to the right as follows: X.sub.0b.sbsb.1 x.sub.b.sbsb.1.spsb.b.sbsb.2 x.sub.b.sbsb.2.spsb.b.sbsb.3 . . . X.sub.b.sbsb.m-2.spsb.b.sbsb.m-1 X.sub.b.sbsb.m-1.spsb.b.sbsb.m so that a j th index of a coefficient becomes an i th index of a next right adjacent coefficient; and (d) arranging the order the b-subscripts of the m coefficients in ascending order, b 1 b 2 b 3 . . . b m , for indicating the left to right optimal sequence for ordering the m queued access requests indexed 1, 2. . . , m, so that, by following the order of subscripts, the optimal sequence for accessing the memory array yields an access sequence with minimum latency.

Claim 12

The system as in claim 10 wherein the means for minimizing the performance function minimizes the performance function by use of linear programming simplex methods.

Claim 13

The system of claim 7 wherein the scheduling means for parallel servicing of memory access requests by use of parallel channel access combinations that optimize the prescribed performance function criterion comprises means for: (a) forming a set of channel usage column vectors for each queued access request wherein each vector component is binary valued, {0,1}, each component index corresponds to a unique channel index, and each component assumes a value of 1 if the corresponding channel usage is required, otherwise assuming a value of 0; (b) ordering the column vectors to form a usage matrix, A, so that each column index corresponds to the access request queue index associated with the vector; (c) forming a symmetric resource matrix, A T A, wherein all matrix components of A T A having a value of 0 indicate that two vectors, respectively, corresponding to the row and column index of A T A are orthogonal and the corresponding access requests may be performed in parallel, all vectors not identified as orthogonal are non-orthogonal vectors and the corresponding access requests may not be accessed in parallel; and (d) sorting queued memory array access requests into pairs of parallel access requests and nonparallel access requests and forming a new queue of parallel and nonparallel executable access requests ordered in accordance with the optimal sequence except that lower optimal sequence indexed access requests that can be executed in parallel with higher indexed requests are executed in parallel; and (e) executing access requests as determined by the means for sorting queued memory array access requests.

Claim 14

The system of claim 12 wherein additional parallel access to the memory array may be achieved by use of additional scheduling means, comprising means for: (a) reducing the size of resource matrix A by adding orthogonal pairs of usage vectors and forming a new usage vector representative of channel resource usage of both vectors, constructing a new resource matrix A whose columns are the new usage vectors plus the non-orthogonal column vectors of resource matrix A; (b) forming a symmetric resource matrix A T A, wherein all matrix components of value 0 indicate that two vectors corresponding respectively to the row and column index of the value 0 are orthogonal and the corresponding access requests may be performed in parallel, all vectors not identified as orthogonal are non-orthogonal and the corresponding access requests may not be accessed in parallel; (c) sorting queued memory access requests into parallel executable access requests and nonparallel executable access requests in which a new parallel access request is of level three or four corresponding to parallel access by three or four access requests; and (d) optionally repeating, under the scheduling program control, the use of the means for reducing the size of matrix A and the means for forming a symmetric resource matrix, A T A, for identification of additional parallelism if orthogonal usage vectors exist in new matrix A.

Claim 15

The system of claim 6 wherein the translation program controls translation means for translating logical access address data to a physical array access address data set for an array of C channels, using a RAID-0 format, the logical access address data described by a starting block address, n, and a block length parameter, N, indicating the number of contiguous blocks to be accessed, and producing a set of channel indices, {m i }, a set of channel starting addresses, {s m .sbsb.i }, and a set of channel transfer length parameters, {X i (j)}, indicating the number of contiguous blocks to be accessed for each rank, p j , for each channel, for producing a set of physical access address data requiring a minimal set of access commands, the translation means comprises means for: (a) mapping the logical block address information given as the logical starting block, n, and the number of contiguous blocks to be accessed, N, into a set of channel indices, {m i }, by use of the following relationship: m.sub.i =(n+i) mod C where 0≦i≦C-1 is an index representing the order of accessing the channel corresponding to the value of m i ; (b) identifying the first drive, D m .sbsb.i.spsb.,p.sbsb.i, involved in the access, the coordinate parameters (m i , p i ), satisfying the following conditions: M.sub.p.sbsb.i ≦(n+i)/C<M.sub.p.sbsb.i.spsb.+1 where ##EQU18## p i is a rank index, and B k is the number of blocks in rank k; (c) computing a set of starting physical block addresses for each channel, {s m .sbsb.i }, as follows: s.sub.m.sbsb.i =(((n+i)-m.sub.i)/C)-M.sub.p.sbsb.i ; (d) computing the number of blocks to be accessed, x i (0), for each channel, m i , as follows: ##STR6## (e) testing to determine if additional higher ranks are involved in the access by evaluating if: x.sub.i (0)<[N/C]+σ(N mod C-i); (f) computing the number of data blocks in drive D m .sbsb.i.spsb.,p.sbsb.i.spsb.+1, x i (1), if x i (0)<[N/C]+σ(N mod C-i), using the following expression: x.sub.i (1)=max{0, min{[N/C]+σ(N mod C-i)-x.sub.i (0), B.sub.p.sbsb.i.spsb.+1 }}; and (g) testing to determine if additional higher ranks are involved in the access by evaluating if x i (j)>0, where ##STR7## so that if x i (j)>0, x i (j) represents the number of blocks in drive D m .sbsb.i.spsb.,p.sbsb.i.spsb.+j involved in the access.

Claim 16

The system of claim 6 wherein the translation program controls translation means for translating logical access address data to a physical access address data set, for the array of bulk memories having C channels using a RAID-1 partitioned mirrored data format, the logical access address data described by a starting block address, n, and a block length parameter, N, indicating the number of contiguous blocks to be accessed, and producing a set of channel indices, {m i }, a set of channel starting addresses, {s m .sbsb.i }, and a set of channel transfer length parameters, {x i (j)}, indicating the length of access for each rank, p j , involved in the access for each channel, for producing a set of physical access address data requiring a minimal set of access commands, the partitioned memory having a first set of channel and rank coordinates, (m, p), for a first partitioned section of memory, and a second set (m', p') for a second partitioned section of memory, the translation means comprises for the first memory section, using coordinate system (m, p), means for: (a) mapping the logical block address information given as the logical starting block, n, and the number of contiguous blocks to be accessed, N, into a set of channel indices, {m i }, by use of the following relationship: m.sub.i 32 (n+i) mod C where 0≦i≦C-1 is an index representing the order of accessing the channel corresponding to the value of m i ; (b) identifying the first drive, D m .sbsb.i.spsb.,p.sbsb.i, involved in the access, the coordinate parameters (m i , p i ), satisfying the following conditions: M.sub.p.sbsb.i ≦(n+i)/C<M.sub.p.sbsb.i.spsb.+1 where ##EQU19## p i is a rank index, and B k is the number of blocks in rank k; (c) computing a set of starting physical block addresses for each channel, {s m .sbsb.i }, as follows: s.sub.m.sbsb.i =((n+i)-m.sub.i)/C-M.sub.p.sbsb.i ; (d) computing the number of blocks to be accessed, x i (0), for each channel, m i , as follows: x.sub.i (0)=min{([N/C]+σ(N mod C-i)),(B.sub.p.sbsb.i -s.sub.m.sbsb.i)}, where σ(•)=1 for (N mod C-i)>0, and σ(•)=0 otherwise; (e) testing to determine if additional higher ranks are involved in the access by evaluating if: x.sub.i (0)<[N/C]+σ(N mod C-i), and if x i (0) satisfies this condition, computing the number of data blocks in drive D m .sbsb.i.spsb.,p.sbsb.i.spsb.+1, x i (1), using the following expression: x.sub.i (1)=max{0, min{[N/C]+σ(N mod C-i)-x.sub.i (0), B.sub.p.sbsb.i.spsb.+1 }}, and also to determine if additional higher ranks are involved in the access by evaluating if x i (j)>0 where ##STR8## so that if x i (j)>0, x i (j) represents the number of blocks in drive D m .sbsb.i.spsb.,p.sbsb.i.spsb.+j involved in the access; and for the second memory section, using coordinate system (m', p'), means for: (a) mapping the logical block address information given as the logical starting block, n, and the number of contiguous blocks to be accessed, N, into a set of channel indices, {m' i }, by use of the following relationship: m'.sub.i =(n+i) mod C where 0≦i≦C-1 is an index representing the order of accessing the channel corresponding to the value of m' i ; (b) identifying the first drive, D m' .sbsb.i.spsb.,p'.sbsb.i, involved in the access, the coordinate parameters (m i , p i ), satisfying the following conditions: M.sub.p'.sbsb.i ≦(n+i)/C<M.sub.p'.sbsb.i.spsb.+1 where ##EQU20## is a rank index, and B k is the number of blocks in rank k; (c) computing a set of starting physical block addresses for each channel, {s m' .sbsb.i }, as follows: s.sub.m'.sbsb.i =((n+i)-m'.sub.i)/C-M.sub.p'.sbsb.i ; (d) computing the number of blocks to be accessed, x i (0), for each channel, m' i , as follows: x.sub.i (0)=min{([N/C]+σ(N mod C-i)),(B.sub.p.sbsb.i -s.sub.m'.sbsb.i)}; (e) testing to determine if additional higher ranks are involved in the access by evaluating if: x.sub.i (0)<[N/C]+σ(N mod C-i), and if x i (0) satisfies this condition, computing the number of data blocks in drive D m' .sbsb.i.spsb.,p'.sbsb.i.spsb.+1, x i (1), using the following expression: x.sub.i (1)=max{0,min{[N/C]+σ(N mod C-i)-x.sub.i (0),B.sub.p'.sbsb.i.spsb.+1 }}, and also to determine if additional higher ranks are involved in the access by evaluating if x i (j)>0, where ##STR9## so that if x i (j)>0, x i (j) represents the number of blocks in drive D m' .sbsb.i.spsb.,p'.sbsb.i.spsb.+j involved in the access.

Claim 17

The system of claim 15 wherein the division of logical array memory is along a rank boundary.

Claim 18

The system of claim 15 wherein the division of logical array memory is along a channel boundary.

Claim 19

The system of claim 1 wherein the translation program controls translation means for translating logical access address data to a physical array access address data, for an array of C channels and a plurality of rank levels, using a RAID-3 byte striping format, the logical access address data described by a starting block address, n, and a block length parameter, N, indicating the number of blocks to be accessed, and producing a set of rank index, {p j }, a starting address index, s, and a set of transfer length parameters, {x(j)}a, indicating the length of access for each rank, p j , involved in the access, and for producing a set of physical access addresses requiring a minimal set of access commands, the translation means comprising means for: (a) mapping the logical block address, n, into a rank index, p, that represents the first set of drives involved in the data access and satisfies the condition: M.sub.p ≦n<M.sub.p+1 where ##EQU21## M 0 =0 and B k ' is the number of blocks in all memory units in rank k; (b) computing a starting address, s, for use in accessing each memory unit in rank p, using the relationship: s=n-M.sub.p ; (c) computing a number, x(0), indicating how many blocks to access in rank p, where: x(0)=min {N,B.sub.p -s}; (d) testing to determine if additional higher ranks are involved in the access by evaluating if: x(0)<N which, if satisfied, indicates that rank p+1 memory units are involved with starting addresses of 0; (e) determining a number, x(1), indicating the number of blocks in each memory unit of rank p+1 to be accessed as determined by: x(1)=max {0, min {(N-x(0)), B.sub.p+1 }}; and (f) testing to determine if additional higher ranks, p+j, are involved in the access by evaluating if x(j)>0, where ##EQU22## so that if x(j)>0, x(j) represents the number of blocks, beginning at address 0, in all memory units of rank p+j.

Claim 20

The system of claim 6 wherein the translation program controls translation means for translating logical access address data, representative of a starting block index, n, and length index, N, representative of the number of blocks in the access, to a physical array access address data set, for an array of C channels using a RAID-5 block striping format with distributed parity for allowing parallel access operations, the distributed parity blocks located at reserved logical block addresses, n j , where n j satisfies a constraint condition, n j mod C 2 =j(C+1) for j=0,1,2 . . . , C-1, the physical array access address data set includes a set of channel indices, {m i }, a set of channel starting addresses, {s m .sbsb.i }, and a set of channel transfer length parameters, {x i (j)}, indicating the number of blocks in rank j and channel m i that are involved in the access, for producing a set of physical access address data requiring a minimal set of access commands, the translation means comprises means for: (a) defining a modified logical block address index, n, and a modified length index, N, satisfying the following conditions: n'=n+P(n) N'=N+P(n+N-1)-P(n) where ##STR10## (b) mapping the logical block address information given as the logical starting block, n', and the number of contiguous blocks to be accessed, N', into a set of channel indices, {m i }, by use of the following relationship: m.sub.i =(n'+i) mod C where 0≦i≦C-1 is an index representing the order of accessing the channel corresponding to the value of m i ; (c) identifying the first drive, D m .sbsb.i.spsb.,p i , involved in the access, the coordinate parameters (m i , p i ), satisfying the following conditions: M.sub.p.sbsb.i ≦(n'+i)/C<M.sub.p.sbsb.i.spsb.+1 where ##EQU23## p i is a rank index, and B k is the number of blocks in rank k; (d) computing a set of starting physical block addresses for each channel, {s m .sbsb.i }, as follows: s.sub.m.sbsb.i =((n'+i)-m.sub.i)/C-M.sub.p.sbsb.i ; (e) computing the number of blocks to be accessed, x i (0), for each channel, m i , as follows: x.sub.i (0)=min{([N'/C]+σ(N' mod C-i)),(B.sub.p.sbsb.i -s.sub.m.sbsb.i)}, where σ(•)=1 for (N' mod C-i)>0, and σ(•)=0 otherwise; (f) testing to determine if additional higher ranks are involved in the access by evaluating if x.sub.i (0)<[N'/C]+σ(N' mod C-i), and if x i (0) satisfies this condition, computing the number of data blocks in drive D m .sbsb.i.spsb.,p.sbsb.i.spsb.+1, x i (1), using the expression x.sub.i (1)=max{0,min{[N'/C]+σ(N' mod C-i)-x.sub.i (0),B.sub.p.sbsb.i.spsb.+1 }}, and to determine if additional higher ranks are involved in the access by evaluating if x i (j)>0, where ##STR11## so that if x i (j)>0, x i (j) represents the number of blocks in drive D m .sbsb.i.spsb.,p.sbsb.i.spsb.+j involved in the access.

Claim 21

The system of claim 18 wherein the translation means for translating logical access address data to a physical array access address data set further comprises means for determining that block k i of drive D m .sbsb.i.spsb.,p.sbsb.i is a parity block, block k i is a parity block if, and only if, the following expression is true: (C(M.sub.pi +k.sub.i)+m.sub.i)mod C.sup.2 =m.sub.i (C+1).

Claim 30

The method of claim 24 further comprises a step for identifying that block k i of drive D m .sbsb.i.spsb.,p.sbsb.i is a parity block by evaluating if the following expression is true, (C(M.sub.pi +k.sub.i)+m.sub.i)mod C.sup.2 =m(C+1), which is only true when k i is a parity block.

Claim 33

The method of claim 26 wherein the step of computing the minimum latency order for accessing m queued requests, the requests indexed from 1 to m, comprises: (a) prescribing a performance function, D, representative of the latency for all possible sequential orders of accessing the queued set of m host access requests to the memory array, where ##EQU29## n 0 +N 0 is an initial address corresponding to a last address used to access memory, n i is a memory array address to the i th queued memory array access request, N i is a memory array block size of the i th queued memory array access request, and x i ,j is a binary valued coefficient, {0,1 }, which indicates, when x i ,j =1, that an i th queued memory access is followed by a j th queued memory access; (b) minimizing the performance function, D, subject to a set of conditions as follows: ##EQU30## (c) ordering the set of m coefficients, {x ij }, obtained in step (b) beginning with x 0b .sbsb.1, and proceeding to the right as follows: x.sub.0b.sbsb.1 x.sub.b.sbsb.2.spsb.b.sbsb.2 x.sub.b.sbsb.2.spsb.b.sbsb.3 . . . x.sub.b.sbsb.m-1.spsb.b.sbsb.m so that a j th index of a coefficient becomes an i th index of a next right adjacent coefficient; and (d) arranging the order of the b-subscript of the m coefficients in ascending order, b 1 b 2 b 3 . . . b m , for indicating the left to right sequence for ordering the m queued access requests indexed 1,2 . . . , m, so that, by following the order of subscripts, an optimized sequence for accessing the memory array yields an access sequence with minimum latency.

Claim 34

The method of claim 26 wherein the step of computing the minimum latency order for accessing queued requests, indexed 1 to m, so that a bounded latency for all queued memory array access requests is ensured by counting the number of times a particular access request has been rescheduled without execution, the method comprises: (a) prescribing a performance function, D, representative of the latency for all possible sequential orders of accessing the queued set of m host system access requests to the memory array, where ##EQU31## n 0 +N 0 is an initial address corresponding to a last physical address used to access memory, n i is a memory array physical address to the i th queued memory access address, N i is a parameter indicating the number of blocks to be accessed beginning at address n i , x i ,j is a binary valued coefficient, {0,1 }, which indicates, when x ij =1, that an i th queued memory access is followed by a j th queued memory access, and 2 -dj is a binary parameter scaling factor in which d j is a count of the number of times the j th access request has been rescheduled without execution; (b) minimizing the performance function, D, subject to a set of conditions as follows: ##EQU32## (c) ordering the set of m coefficients, {x ij }, obtained in step (b) beginning with x 0b .sbsb.1, and proceeding to the right as follows: x.sub.0b.sbsb.1 x.sub.b.sbsb.1.spsb.b.sbsb.2 x.sub.b.sbsb.2.spsb.b.sbsb.3 ... x.sub.b.sbsb.m-2.spsb.b.sbsb.m-1 x.sub.b.sbsb.m-1.spsb.b.sbsb.m so that a j th index of a coefficient becomes an i th index of a next right adjacent coefficient; and (d) arranging the order the b-subscripts of the m coefficients in ascending order, b 1 b 2 b 3 . . . b m , for indicating the left to right optimal sequence for ordering the m queued access requests indexed 1,2 . . . , m, so that, by following the order of subscripts, the optimal sequence for accessing the memory array yields an access sequence with minimum latency.

Claim 35

The method of claim 26 wherein the step of determining channel bus resource usage of the queued access requests and identifying queued access requests that can be done in parallel, further comprises: (a) forming a set of channel usage column vectors, for each queued access request wherein each vector component is binary valued, {0, 1}, each component index corresponds to a unique channel index, and each component assumes a value of 1 if the corresponding channel usage is required, otherwise assuming a value of 0; (b) ordering the column vectors, to form a usage matrix, A, so that each column index corresponds to the access request queue index associated with the vector; and (c) forming a symmetric resource matrix, A T A, wherein all matrix components of A T A having a value of 0 indicate that two vectors, respectively corresponding to the row and column index of A T A are orthogonal and the corresponding access requests may be performed in parallel, all vectors not identified as orthogonal are non-orthogonal vectors and the corresponding access requests may not be accessed in parallel.

Claim 36

The method of claim 29 wherein additional parallel access to the memory array may be achieved by the additional steps comprising: (a) reducing the size of resource matrix A by adding orthogonal pairs of usage vectors and forming a new usage vector representative of channel resource usage of both vectors, constructing a new resource matrix A whose columns are the new usage vectors and the non-orthogonal column vectors of resource matrix A; (b) forming a symmetric resource matrix A T A, wherein all matrix components of value 0 indicate that two vectors corresponding to the row and column index of the value 0 are orthogonal and the corresponding access requests may be performed in parallel, all vectors not identified as orthogonal are non-orthogonal and the corresponding access requests may not be accessed in parallel; (c) sorting queued memory access requests into parallel executable access requests and nonparallel executable access requests in which a new parallel access request is of level three or four corresponding to parallel access by three or four access requests; and (d) repeating steps (a) and (b) for identification of additional parallelism if orthogonal usage vectors exist in new matrix A, if desired, otherwise terminating the process.

Claim 37

The system of claim 1 further comprising a system fault monitor that comprises: (a) monitoring means for monitoring and reporting the health and status of the bulk memory units, and of the memory array controller hardware including fans and power supplies; and (b) a single-wire serial bus coupled to the monitoring means and to the microprocessor controller for reporting the health and status of the bulk memory units and of the memory array controller hardware.

Claim 38

The system of claim 31 further comprising an alarm controller unit that comprises a set of relays whose states represent the health and status of selected elements of the control system, the states being externally accessible.