Patent US4080603A successfully refreshed from Google Patents.
US5367766A
Expired / Lapsed
US
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Ultra high density integrated circuit packages method
Assignee: Entorian Technologies Inc
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Filing: 1993-04-05
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Granted: 1994-11-29
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Expires: 2013-04-05
Abstract
Abstract Thin and durable level-one and level-two integrated circuit packages are provided. A thin and durable level-one package is achieved in one method involving a molding technique of evenly applying molding compound to an integrated circuit die element. The casing surrounding a die element may be reduced or eliminated in part to thin the level-one package provided any necessary steps are taken to ensure the integrity of the package. Moisture-barriers, as an example, may be provided to the upper and/or lower surfaces of the thin level-one package. Additionally, a thin level-one package may also be constructed with one or more metal layers to prevent warpage. These level-one packages may be aligned in a stacked configuration to form a thin and durable horizontal level-two package. Various thermal conductors may be thermally coupled to the level-two package to help dissipate heat.
Inventors
- 👤 Carmen D. Burns
- 👤 Jerry Roane
- 👤 James W. Cady
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:30
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/01; H10W74/016; H05; H05K; H05K7/00; H05K7/02; H05K7/023; H10W40/00; H10W40/70; H10W40/77; H10W40/778; H10W42/00; H10W90/00; H10W70/00; H10W70/40; H10W70/60; H10W72/00; H10W72/801; H10W90/20; H10W90/288; Y; Y10; Y10S; Y10S438/00; Y10S438/977; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155; Y10T29/49158
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
61 words
A method of forming a thin and durable integrated circuit element comprising the steps of: (a) providing an integrated circuit element formed in a semiconductor substrate, said integrated circuit element having an upper surface, a lower surface and a perimeter wall; and (b) reducing the height of said perimeter wall of said integrated circuit die element by lapping said lower surface.
Claim 2
Independent Claim
61 words
A method of forming a thin and durable integrated circuit element comprising the steps of: (a) providing an integrated circuit element formed in a semiconductor substrate, said integrated circuit element having an upper surface, a lower surface and a perimeter wall; and (b) reducing the height of said perimeter wall of said integrated circuit die element by lapping said lower surface.
Claim 3
Dependent Claim
36 words
The method of claim 1, wherein said lapping of said lower surface continues until said height of said perimeter wall is less than approximately 10.5 mils, but is greater than or equal to approximately 3 mils.
Claim 4
Independent Claim
122 words
A method of forming a thin and durable integrated circuit package comprising the steps of: (a) placing a substantially planar integrated circuit element formed in a semiconductor substrate in a mold cavity having a ceiling, a floor, and a perimeter wall; (b) supporting said integrated circuit element at its upper or lower surfaces with a plurality of support pins extending from the floor or ceiling surfaces of the cavity to contact and support said integrated circuit die element in a position substantially parallel to the floor or ceiling of the mold cavity; (c) transferring molding compound into said mold cavity; (d) allowing said molding compound to set and become hardened casing; and (e) removing said integrated circuit package from said mold cavity.
Claim 5
Independent Claim
122 words
A method of forming a thin and durable integrated circuit package comprising the steps of: (a) placing a substantially planar integrated circuit element formed in a semiconductor substrate in a mold cavity having a ceiling, a floor, and a perimeter wall; (b) supporting said integrated circuit element at its upper or lower surfaces with a plurality of support pins extending from the floor or ceiling surfaces of the cavity to contact and support said integrated circuit die element in a position substantially parallel to the floor or ceiling of the mold cavity; (c) transferring molding compound into said mold cavity; (d) allowing said molding compound to set and become hardened casing; and (e) removing said integrated circuit package from said mold cavity.
Claim 6
Dependent Claim
20 words
The method of claim 3, wherein said pins are formed integrally with the floor or ceiling of said mold cavity.
Claim 7
Dependent Claim
25 words
The method of claim 4, further comprising the step of filling in the cavities in said casing formed by said pins, with a protective coating.
Claim 8
Dependent Claim
53 words
The method of claim 3, wherein said pins support the integrated circuit die element at either its upper surface or its lower surface but not both surfaces, and wherein molding compound is injected into the cavity so as to apply fluid pressure to the die surface opposite the surface supported by said pins.
Claim 9
Dependent Claim
39 words
The method of claim 4, wherein said pins are retractable, and wherein after the molding compound is transferred into said mold cavity and begins to harden but before the molding compound is fully set up, said pins are retracted.
Claim 10
Dependent Claim
16 words
The method of claim 3, wherein said pins are formed integrally with said integrated circuit element.
Claim 11
Independent Claim
94 words
A method of forming a thin and durable integrated circuit package comprising the steps of: (a) placing a substantially planar integrated circuit element in a mold cavity having a ceiling, a floor, and a perimeter wall, such that the lower surface of said integrated circuit element contacts said floor of said mold cavity; (b) transferring molding compound into said mold cavity; (c) allowing said molding compound to set until it becomes hardened casing; (d) removing said integrated circuit element; and (e) adhering a metal layer to the lower surface of said integrated circuit element.
Claim 12
Independent Claim
94 words
A method of forming a thin and durable integrated circuit package comprising the steps of: (a) placing a substantially planar integrated circuit element in a mold cavity having a ceiling, a floor, and a perimeter wall, such that the lower surface of said integrated circuit element contacts said floor of said mold cavity; (b) transferring molding compound into said mold cavity; (c) allowing said molding compound to set until it becomes hardened casing; (d) removing said integrated circuit element; and (e) adhering a metal layer to the lower surface of said integrated circuit element.
Claim 13
Independent Claim
75 words
A method of forming a thin and durable integrated circuit package, comprising the steps of: (a) providing an integrated circuit element formed in a semiconductor substrate, said integrated circuit element having an upper surface, a lower surface, and a perimeter wall; (b) providing a protective casing layer surrounding said upper surface and said perimeter wall of said integrated circuit element; and (c) adhering a metal layer to said lower surface of said integrated circuit element.
Claim 14
Independent Claim
75 words
A method of forming a thin and durable integrated circuit package, comprising the steps of: (a) providing an integrated circuit element formed in a semiconductor substrate, said integrated circuit element having an upper surface, a lower surface, and a perimeter wall; (b) providing a protective casing layer surrounding said upper surface and said perimeter wall of said integrated circuit element; and (c) adhering a metal layer to said lower surface of said integrated circuit element.
Claim 15
Independent Claim
136 words
A method of forming a thin and durable integrated circuit package comprising the steps of: (a) providing an integrated circuit element formed in a semiconductor substrate, said integrated circuit element having an upper surface, a lower surface, and a perimeter wall; (b) applying a metal layer to said lower surface of said integrated circuit element by use of an adhesive; (c) placing the integrated circuit element having said metal layer on its lower surface in a mold cavity, said mold cavity having a ceiling, a floor, and a perimeter wall, such that said metal layer of said integrated circuit element contacts said floor of said mold cavity; (d) transferring molding compound into said mold cavity; (e) allowing said molding compound to set and become hardened casing; and removing said integrated circuit package from said mold cavity.
Claim 16
Independent Claim
136 words
A method of forming a thin and durable integrated circuit package comprising the steps of: (a) providing an integrated circuit element formed in a semiconductor substrate, said integrated circuit element having an upper surface, a lower surface, and a perimeter wall; (b) applying a metal layer to said lower surface of said integrated circuit element by use of an adhesive; (c) placing the integrated circuit element having said metal layer on its lower surface in a mold cavity, said mold cavity having a ceiling, a floor, and a perimeter wall, such that said metal layer of said integrated circuit element contacts said floor of said mold cavity; (d) transferring molding compound into said mold cavity; (e) allowing said molding compound to set and become hardened casing; and removing said integrated circuit package from said mold cavity.
Claim 17
Dependent Claim
24 words
The method of claim 11, wherein the surface of said metal layer which is to be applied to said integrated circuit element is rough.
Claim 18
Dependent Claim
22 words
The method of claim 11, wherein the surface of said metal layer to be applied to said integrated circuit element is notched.
Claim 19
Independent Claim
126 words
A method of forming a thin and durable integrated circuit package, comprising the steps of: (a) providing an integrated circuit element formed in a semiconductor substrate, said integrated circuit element having an upper surface, a lower surface, and a perimeter wall; (b) providing a protective casing layer surrounding said upper surface and said perimeter wall of said integrated circuit element, said protective casing layer having an upper surface and a perimeter wall; (c) adhering a metal layer ribbon to said upper surface of said protective casing layer; (d) holding said metal layer ribbon in tension; (e) thinning said integrated circuit element by lapping said lower surface of said integrated circuit element; and (f) adhering a metal layer to said lower surface of said integrated circuit element.
Claim 20
Independent Claim
126 words
A method of forming a thin and durable integrated circuit package, comprising the steps of: (a) providing an integrated circuit element formed in a semiconductor substrate, said integrated circuit element having an upper surface, a lower surface, and a perimeter wall; (b) providing a protective casing layer surrounding said upper surface and said perimeter wall of said integrated circuit element, said protective casing layer having an upper surface and a perimeter wall; (c) adhering a metal layer ribbon to said upper surface of said protective casing layer; (d) holding said metal layer ribbon in tension; (e) thinning said integrated circuit element by lapping said lower surface of said integrated circuit element; and (f) adhering a metal layer to said lower surface of said integrated circuit element.
Claim 21
Independent Claim
143 words
A method of forming a thin and durable integrated circuit package, comprising the steps of: (a) providing an integrated circuit element formed in a semiconductor substrate, said integrated circuit element having an upper surface, a lower surface, and a perimeter wall; (b) providing a protective casing layer surrounding said upper surface and said perimeter wall of said integrated circuit element, said protective casing layer having an upper surface and a perimeter wall; (c) lapping the upper surface of said protective casing layer uniformly to produce a smooth planar surface; (d) adhering a metal layer ribbon to said upper surface of said protective casing layer; (e) holding said metal layer ribbon in tension; (f) thinning said integrated circuit element by lapping said lower surface of said integrated circuit element; and (g) adhering a metal layer to said lower surface of said integrated circuit element.
Claim 22
Independent Claim
143 words
A method of forming a thin and durable integrated circuit package, comprising the steps of: (a) providing an integrated circuit element formed in a semiconductor substrate, said integrated circuit element having an upper surface, a lower surface, and a perimeter wall; (b) providing a protective casing layer surrounding said upper surface and said perimeter wall of said integrated circuit element, said protective casing layer having an upper surface and a perimeter wall; (c) lapping the upper surface of said protective casing layer uniformly to produce a smooth planar surface; (d) adhering a metal layer ribbon to said upper surface of said protective casing layer; (e) holding said metal layer ribbon in tension; (f) thinning said integrated circuit element by lapping said lower surface of said integrated circuit element; and (g) adhering a metal layer to said lower surface of said integrated circuit element.
References Cited (Backward Citations)
US2241493A
Cited
US3436604A
Cited
US3713893A
Cited
US3614546A
Cited
US3739462A
Cited
US3746934A
Cited
US4222516A
Cited
US4103318A
Cited
US4158745A
Cited
US4321418A
Cited
US4288841A
Cited
JPS5731166A
Cited
US4437235A
Cited
US4451973A
Cited
US4501960A
Cited
US4525921A
Cited
JPS5896756A
Cited
JPS58112348A
Cited
US4530152A
Cited
US4633573A
Cited
US4521828A
Cited
US4630172A
Cited
JPS60180150A
Cited
US4722060A
Cited
US4884237A
Cited
US4680617A
Cited
US4733461A
Cited
JPS61163652A
Cited
JPS61219143A
Cited
US4862245A
Cited
US4821148A
Cited
US5049527A
Cited
US4823234A
Cited
US4684975A
Cited
US4763188A
Cited
JPS6353959A
Cited
US4888307A
Cited
US4878106A
Cited
JPS63153849A
Cited
US4839717A
Cited
US4829403A
Cited
US4855868A
Cited
JPS63187652A
Cited
US4862249A
Cited
US4953005A
Cited
US4796078A
Cited
US4833568A
Cited
US4891789A
Cited
US4994411A
Cited
EP0340100A1
Cited
US5147822A
Cited
US4956694A
Cited
US5108553A
Cited
US4953060A
Cited
US5057906A
Cited
US5089876A
Cited
US4948645A
Cited
US5155068A
Cited
US5200362A
Cited
US5223739A
Cited
US5014113A
Cited
US4997517A
Cited
US5151599A
Cited
US5041015A
Cited
US5264990A
Cited
US5139969A
Cited
US5065277A
Cited
US5138434A
Cited
US5099393A
Cited
US5086018A
Cited
US5138430A
Cited
US5214845A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-28 | 1998-05-30 | 1998-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-28 | 2002-05-30 | 2002-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-28 | 2006-05-30 | 2006-11-29 | $7700.00 | Window Closed / Lapsed |