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US5371702A
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US
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Block erasable nonvolatile memory device
Assignee: Toshiba Corp
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Filing: 1993-03-05
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Granted: 1994-12-06
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Expires: 2013-03-05
Abstract
Abstract In response to a plurality of address signal input from the outside in sequence, an erase information inputting section controls an erase information holding section corresponding to the batch erase block to be erased so as to hold an erase information data. By repeating this operation in sequence, the erase information data are stored in the erase information holding sections corresponding to the plural batch erase blocks to be erased. Successively, on the basis of the erase information data stored in the erase information holding sections, block erasing sections are activated to erase all the nonvolatile memory cells of each of the corresponding blocks where the erase information data are held. As a result, the erasure operation is achieved for all the batch erase blocks corresponding to the erase information holding sections in each of which the erase information data is held, so that a plurality of batch erase blocks can be erased simulataneously, thus reducing the erasure time, as compared with the prior art memory device.
Inventors
- 👤 Hiroto Nakai
- 👤 Hideo Kato
- 👤 Kaoru Tokushige
- 👤 Masamichi Asano
- 👤 Kazuhisa Kanazawa
- 👤 Toshio Yamamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 03:35
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
200 words
A nonvolatile semiconductor memory device, comprising: a plurality of batch erase blocks each composed of a plurality of simultaneously erasable nonvolatile memory cells; block selecting means for selecting one of a plurality of said batch erase blocks and for outputting a block select signal to a node corresponding to each of the batch erase blocks; a plurality of erase information holding means provided for each of the batch erase blocks, for holding erase information of each of the batch erase blocks and for transmitting the block select signal to the corresponding batch erase block in a read operation; erase information inputting means for allowing the erase information to be held by said erase information holding means corresponding to said batch erase block selected by said block selecting means; and a plurality of memory cell selecting means provided for each of said batch erase blocks, for selecting the nonvolatile memory cells in the corresponding batch erase block in response to the block select signal on the node in the read operation, and for erasing all the nonvolatile memory cells of the corresponding batch erase blocks when the erase information is held by said corresponding erase information holding means in erasure operation.
Claim 2
Dependent Claim
200 words
A nonvolatile semiconductor memory device, comprising: a plurality of batch erase blocks each composed of a plurality of simultaneously erasable nonvolatile memory cells; block selecting means for selecting one of a plurality of said batch erase blocks and for outputting a block select signal to a node corresponding to each of the batch erase blocks; a plurality of erase information holding means provided for each of the batch erase blocks, for holding erase information of each of the batch erase blocks and for transmitting the block select signal to the corresponding batch erase block in a read operation; erase information inputting means for allowing the erase information to be held by said erase information holding means corresponding to said batch erase block selected by said block selecting means; and a plurality of memory cell selecting means provided for each of said batch erase blocks, for selecting the nonvolatile memory cells in the corresponding batch erase block in response to the block select signal on the node in the read operation, and for erasing all the nonvolatile memory cells of the corresponding batch erase blocks when the erase information is held by said corresponding erase information holding means in erasure operation.
Claim 3
Dependent Claim
72 words
The nonvolatile semiconductor memory device according to claim 1, wherein each of said batch erase blocks has a plurality of NAND bundles arranged in a row direction and wherein said memory cell selecting means provides a low voltage control gate signal for selecting a memory cell of each of said NAND bundles and provides a high voltage control gate signal to other memory cells of said NAND bundles in said read operation.
Claim 4
Dependent Claim
50 words
The nonvolatile semiconductor memory device according to claim 1, wherein said memory cell selecting means applies an erase voltage to control electrodes of each of the memory cells in the batch erase blocks whenever the erase information is held by said corresponding erase information holding means in an erasure operation.
Claim 5
Dependent Claim
234 words
A nonvolatile semiconductor memory device, comprising: a plurality of batch erase blocks each composed of a plurality of simultaneously erasable nonvolatile memory cells; a plurality of decoding means provided for each of the batch erase blocks, each decoding means outputting a decoded signal in response to internal address signals; a plurality of erase information holding means provided for each of the batch erase blocks, each erase information holding means holding binary data corresponding to erase information of each of the batch erase blocks and outputting an erase signal corresponding to said binary data; erase information inputting means for allowing the erase information to be held by said erase information holding means in a sequence; a plurality of signal selecting means provided for each of the batch erase blocks, each signal selecting means transmitting said decoded signal from said decoding means to an output terminal in a read operation and transmitting said erase signal from said erase information holding means to said output terminal in an erasure operation; and a plurality of memory cell selecting means provided for each of said batch erase blocks, for selecting the nonvolatile memory cells in the corresponding batch erase block in response to the signal on said output terminal in the read operation, and for erasing the nonvolatile memory cells in the corresponding batch erase blocks in response to the signal on said output terminal in the erasure operation.
Claim 6
Dependent Claim
234 words
A nonvolatile semiconductor memory device, comprising: a plurality of batch erase blocks each composed of a plurality of simultaneously erasable nonvolatile memory cells; a plurality of decoding means provided for each of the batch erase blocks, each decoding means outputting a decoded signal in response to internal address signals; a plurality of erase information holding means provided for each of the batch erase blocks, each erase information holding means holding binary data corresponding to erase information of each of the batch erase blocks and outputting an erase signal corresponding to said binary data; erase information inputting means for allowing the erase information to be held by said erase information holding means in a sequence; a plurality of signal selecting means provided for each of the batch erase blocks, each signal selecting means transmitting said decoded signal from said decoding means to an output terminal in a read operation and transmitting said erase signal from said erase information holding means to said output terminal in an erasure operation; and a plurality of memory cell selecting means provided for each of said batch erase blocks, for selecting the nonvolatile memory cells in the corresponding batch erase block in response to the signal on said output terminal in the read operation, and for erasing the nonvolatile memory cells in the corresponding batch erase blocks in response to the signal on said output terminal in the erasure operation.
Claim 7
Dependent Claim
48 words
The nonvolatile semiconductor memory device according to claim 4, wherein each of said erase information holding means includes latch means and switching means, either one of said switching means selected by said decoding means transmitting erase data stored in said latch means corresponding to said selected switching means.
Claim 8
Dependent Claim
31 words
The nonvolatile semiconductor memory device according to claim 5, wherein said erase information inputting means generating said erase data on an erase data input line commonly connected to said switching means.
Claim 9
Dependent Claim
32 words
The nonvolatile semiconductor memory device according to claim 6, which further comprises erase binary data outputting means for outputting contents of said erase information holding means on said erase data input line.
Claim 10
Dependent Claim
46 words
The nonvolatile semiconductor memory device according to claim 4, wherein said each of said plurality of erase information holding means includes latch means and switching means, either one of said switching means transmitting said decoded signal from said corresponding decoding means to said corresponding latch means.
Claim 11
Dependent Claim
32 words
The nonvolatile semiconductor memory device according to claim 8, which further comprises erase binary data outputting means for outputting contents of said erase information holding means on an erase data output line.
Claim 12
Dependent Claim
149 words
A nonvolatile semiconductor memory device, comprising: a plurality of batch erase blocks each composed of a plurality of simultaneously erasable nonvolatile memory cells; a plurality of erase information holding means provided for each of the batch erase blocks, for holding erase information of each of the batch erase blocks; erase information inputting means for allowing the erase information to be held by said erase information holding means; a plurality of erasing means provided for each of said batch erase blocks, for applying an erase voltage to a control electrode of each of the nonvolatile memory cells of the corresponding batch erase block, whenever the erase information is held by said corresponding erase information holding means in an erasure operation; and erase information reading means for outputting erase information data of selected one of said erase information holding means on a common line connected to said erase information holding means.
Claim 13
Dependent Claim
149 words
A nonvolatile semiconductor memory device, comprising: a plurality of batch erase blocks each composed of a plurality of simultaneously erasable nonvolatile memory cells; a plurality of erase information holding means provided for each of the batch erase blocks, for holding erase information of each of the batch erase blocks; erase information inputting means for allowing the erase information to be held by said erase information holding means; a plurality of erasing means provided for each of said batch erase blocks, for applying an erase voltage to a control electrode of each of the nonvolatile memory cells of the corresponding batch erase block, whenever the erase information is held by said corresponding erase information holding means in an erasure operation; and erase information reading means for outputting erase information data of selected one of said erase information holding means on a common line connected to said erase information holding means.
Claim 14
Dependent Claim
40 words
The nonvolatile semiconductor memory device according to claim 10, which further comprises erase verify operation control means for selectively accomplishing an erase verify read operation for memory cells in erased batch erase blocks in response to said erase information data.
Claim 15
Dependent Claim
246 words
A nonvolatile semiconductor memory device, comprising: a plurality of batch erase blocks each composed of a plurality of simultaneously erasable nonvolatile memory cells; a plurality of erase information holding means provided for each of the batch erase blocks, for holding erase information of each of the batch erase blocks; erase information inputting means for allowing the erase information to be held by said erase information holding means; a plurality of erasing means provided for each of said batch erase blocks, for applying an erase voltage to each of the nonvolatile memory cells of the corresponding batch erase block, whenever the erase information is held by said corresponding erase information holding means in an erasure operation; and erase verify operation control means for providing a selective erase verify operation for only memory cells in erased batch erase blocks in response to said erase information with following sequential functions: an erased block searching function of searching an erased batch erase block address by reading said erase information from said erase information holding means and setting an internal address for said erased batch erase block address, and an erase verify function of reading memory cells data in the batch erase block designated by said internal address and generating a pass-fail signal in response to said read out memory cells data, if said pass-fail signal shows an unsuccessful erase operation, performing a re-erase operation and if said pass-fail signal shows successful erase operation, performing a next erased block searching operation.
Claim 16
Dependent Claim
246 words
A nonvolatile semiconductor memory device, comprising: a plurality of batch erase blocks each composed of a plurality of simultaneously erasable nonvolatile memory cells; a plurality of erase information holding means provided for each of the batch erase blocks, for holding erase information of each of the batch erase blocks; erase information inputting means for allowing the erase information to be held by said erase information holding means; a plurality of erasing means provided for each of said batch erase blocks, for applying an erase voltage to each of the nonvolatile memory cells of the corresponding batch erase block, whenever the erase information is held by said corresponding erase information holding means in an erasure operation; and erase verify operation control means for providing a selective erase verify operation for only memory cells in erased batch erase blocks in response to said erase information with following sequential functions: an erased block searching function of searching an erased batch erase block address by reading said erase information from said erase information holding means and setting an internal address for said erased batch erase block address, and an erase verify function of reading memory cells data in the batch erase block designated by said internal address and generating a pass-fail signal in response to said read out memory cells data, if said pass-fail signal shows an unsuccessful erase operation, performing a re-erase operation and if said pass-fail signal shows successful erase operation, performing a next erased block searching operation.
Claim 17
Dependent Claim
255 words
A nonvolatile semiconductor memory device, comprising: a plurality of batch erase blocks each composed of a a plurality of batch erase blocks each composed of a plurality of simultaneously erasable nonvolatile memory device; a plurality of erase information holding means provided for each of the batch erase blocks, for holding erase information of each of the batch erase blocks; erase information inputting means for allowing the erase information to be held by said erase information holding means; a plurality of erasing means provided for each of said batch erase blocks, for applying an erase voltage to each of the nonvolatile memory cells in the selected batch erase block in which the erase information is held by said corresponding erase information holding means in an erasure operation; and erase operation control means for checking memory cell data in the selected batch erase blocks having has the erase information held in said corresponding erase information holding means with following sequential functions: an erase verify function of searching the address of said selected batch erase blocks by reading the erase information from said each erase information holding means and reading said memory cell data in said selected batch erase blocks, if erase successful memory cell data is read out from a pre-determined number of said selected batch erase blocks, changing the erase information in erase information holding means in the batch erase blocks, having only erase successful memory cells, and a re-erase function of erasing memory cells in the batch erase blocks having an erase unsuccessful memory cell.
Claim 18
Dependent Claim
255 words
A nonvolatile semiconductor memory device, comprising: a plurality of batch erase blocks each composed of a a plurality of batch erase blocks each composed of a plurality of simultaneously erasable nonvolatile memory device; a plurality of erase information holding means provided for each of the batch erase blocks, for holding erase information of each of the batch erase blocks; erase information inputting means for allowing the erase information to be held by said erase information holding means; a plurality of erasing means provided for each of said batch erase blocks, for applying an erase voltage to each of the nonvolatile memory cells in the selected batch erase block in which the erase information is held by said corresponding erase information holding means in an erasure operation; and erase operation control means for checking memory cell data in the selected batch erase blocks having has the erase information held in said corresponding erase information holding means with following sequential functions: an erase verify function of searching the address of said selected batch erase blocks by reading the erase information from said each erase information holding means and reading said memory cell data in said selected batch erase blocks, if erase successful memory cell data is read out from a pre-determined number of said selected batch erase blocks, changing the erase information in erase information holding means in the batch erase blocks, having only erase successful memory cells, and a re-erase function of erasing memory cells in the batch erase blocks having an erase unsuccessful memory cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-05 | 1998-06-06 | 1998-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-05 | 2002-06-06 | 2002-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-05 | 2006-06-06 | 2006-12-06 | $7700.00 | Window Closed / Lapsed |