US5372969A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low-RC multi-level interconnect technology for high-performance integrated circuits
Assignee: Texas Instruments Inc
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Filing: 1992-03-03
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Granted: 1994-12-13
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Expires: 2012-03-03
Abstract
Abstract A high-performance "low-RC" multi-level interconnect technology has been conceived for advanced sub-0.5 μm semiconductor technologies. The proposed structure and fabrication process has a number of significant characteristics: (i) compatible with various metal systems (Al, Cu, W, etc.), (ii) free-space interlevel dielectrics; (iii) compatible with standard semiconductor fabrication processes, (iv) excellent mechanical stability; and (v) compatible with hermetically sealed chip packaging techniques. Compared with an Al-based conventional interconnect technology, the new interconnect system can reduce the "RC" delay by a factor of - 6. The proposed interconnect technology offers major chip performance improvements such as lower power dissipation and higher operating frequencies. This technology is based on a manufacturable process to fabricate multilevel interconnect with free-space dielectrics and a technology scaling enabler.
Inventors
- 👤 Mehrdad M. Moslehi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:29
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/072; H10W20/074; H10W20/076; H10W20/40; H10W20/41; H10W20/42; H10W20/435; H10W20/45; H10W20/46; H10W20/47; H10W20/495
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
149 words
A process for forming a structure having a multi-level metalization on an integrated circuit formed on a substrate having a substantially planar surface comprising the steps of: (a) forming, as part of one level, a plurality of dielectric islands in a desired island pattern on said substantially planar surface; (b) surrounding said islands with a supporting material; (c) selectively forming electrically conductive vias and trenches in said islands and leaving a substantially planar surface; (d) depositing an interlevel layer over said planar surface to produce a new substantially planar surface; and (e) repeating steps (a) through (d), where said substantially planar surface in step (a) is said new substantially planar surface created in the previously executed step (d), a selected number of times with the projection of said island pattern in any one level being non-congruent with said island pattern of the level immediately below said any one level.
Claim 2
Dependent Claim
149 words
A process for forming a structure having a multi-level metalization on an integrated circuit formed on a substrate having a substantially planar surface comprising the steps of: (a) forming, as part of one level, a plurality of dielectric islands in a desired island pattern on said substantially planar surface; (b) surrounding said islands with a supporting material; (c) selectively forming electrically conductive vias and trenches in said islands and leaving a substantially planar surface; (d) depositing an interlevel layer over said planar surface to produce a new substantially planar surface; and (e) repeating steps (a) through (d), where said substantially planar surface in step (a) is said new substantially planar surface created in the previously executed step (d), a selected number of times with the projection of said island pattern in any one level being non-congruent with said island pattern of the level immediately below said any one level.
Claim 3
Dependent Claim
22 words
The process according to claim 1 additionally including the step of: (f) removing, after step (e), said islands and said interlevel layers.
Claim 4
Dependent Claim
15 words
A process as recited in claim 1 wherein each said island pattern is hexagonally shaped.
Claim 5
Dependent Claim
25 words
A process as recited in claim 1 wherein said substrate is selected from the group of semiconductor materials consisting of silicon, gallium arsenide, and germanium.
Claim 6
Dependent Claim
22 words
A process as recited in claim 1 comprising placing a passivation overlayer over the final structure created by steps (a) through (e).
Claim 7
Dependent Claim
113 words
A process as recited in claim 5 wherein said passivation overlayer is formed by the steps comprising: (f) placing a layer of a third dielectric material over the planar surface produced in the last executed step d; (g) etching areas in said third dielectric material according to a desired pattern so as to etch areas in said third dielectric material corresponding to bonding pad locations; (h) forming a bonding pad made of an electrically conductive material at each said bonding pad location; (i) placing a conformal layer over the structure thus formed by the foregoing processing steps; (j) etching said conformal layer so as to remove said conformal layer from said bonding pads.
Claim 8
Dependent Claim
41 words
A process as recited in claim 6 which further includes the steps of: (k) connecting said bonding pads to lead wires; (l) fabricating a hermetically sealed package in a controlled ambient selected from the group consisting of air, nitrogen and vacuum.
Claim 9
Dependent Claim
31 words
A process as recited in claim 1 wherein said electrically conductive vias and trenches are made of a material selected from the group consisting of copper, aluminum, tungsten and their alloys.
Claim 10
Dependent Claim
29 words
A process as recited in claim 1 wherein a glue layer is formed as part of step c between said electrically conductive vias and trenches and said dielectric islands.
Claim 11
Dependent Claim
15 words
The process according to claim 1 wherein said interlevel layer includes a patterned conductive material.
References Cited (Backward Citations)
EP0129476A2
Cited
US4918032A
Cited
JPH01296641A
Cited
JPH0237136A
Cited
JPH0286147A
Cited
US4980034A
Cited
US5000818A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-12 | 1998-06-13 | 1998-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-12 | 2002-06-13 | 2002-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-12 | 2006-06-13 | 2006-12-13 | $7700.00 | Window Closed / Lapsed |