US5378643A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrically programmable non-volatile semiconductor memory device and manufacturing method thereof
Assignee: Mitsubishi Electric Corp
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Filing: 1992-12-31
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Granted: 1995-01-03
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Expires: 2012-12-31
Abstract
Abstract An A-1 transistor type flash EEPROM is disclosed. The memory cell in the EEPROM comprises: a first control gate which is formed, through a first insulating film, on a first channel region formed between a source region and a drain region. A floating gate is formed on the second channel region through a second insulating film and on the first control gate through the first interlayer insulating film. A second control gate is formed on a surface of the floating gate through a second interlayer insulating film. One end of the second control gate and one end of the first control gate are electrically connected to each other through a third control gate, thereby enhancing capacitance between the control gates and the floating gate.
Inventors
- 👤 Natsuo Ajika
- 👤 Hideaki Arima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:35
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
162 words
A method for manufacturing a semiconductor memory device comprising the steps of: forming a source region of second conduction type and a drain region of second conduction type in a semiconductor substrate of first conduction type so that said source region is separated from said drain region by first and second channel regions; forming a first portion of a control gate, on a first insulating film, over said first channel region; forming a floating gate on a second insulating film over said second channel region and on a first interlayer insulating film over said first portion of said control gate; forming a second portion of said control gate over a surface of said floating gate on a second interlayer insulating film; and forming a third portion of said control gate, which connects one end of the second portion of said control gate to one end of said first portion of said control gate, orthogonal with one main surface of the semiconductor substrate.
Claim 2
Independent Claim
162 words
A method for manufacturing a semiconductor memory device comprising the steps of: forming a source region of second conduction type and a drain region of second conduction type in a semiconductor substrate of first conduction type so that said source region is separated from said drain region by first and second channel regions; forming a first portion of a control gate, on a first insulating film, over said first channel region; forming a floating gate on a second insulating film over said second channel region and on a first interlayer insulating film over said first portion of said control gate; forming a second portion of said control gate over a surface of said floating gate on a second interlayer insulating film; and forming a third portion of said control gate, which connects one end of the second portion of said control gate to one end of said first portion of said control gate, orthogonal with one main surface of the semiconductor substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-02 | 1998-07-04 | 1999-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-02 | 2002-07-04 | 2003-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-02 | 2006-07-04 | 2007-01-03 | $7700.00 | Window Closed / Lapsed |