Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a memory matrix including a plurality of data lines, a plurality of word lines and a plurality of read only memory cells which are coupled to the data lines and to the word lines; a row decoder, coupled to the word lines, for selecting one of the word lines in accordance with row address signals; a column decoder for generating a selection signal in accordance with column address signals; a column selector, coupled to said column decoder and to the data lines, for selecting one of the data lines in accordance with the generated selection signal from said column decoder; a column redundant memory matrix including at least one redundant word line, a plurality of redundant data lines and a plurality of electrically programmable memory cells which are coupled to the redundant data lines and to said at least one redundant word line; a column redundant column decoder for generating a redundant selection signal in accordance with the row address signals; a column redundant selector, coupled to the redundant data lines and to said column redundant column decoder, for selecting at least one of the redundant data lines in accordance with the row address signals; column detection means, for detecting coincidence of the column address signals to be supplied to said column decoder with a defective column address signal which indicates a defective data line in said memory matrix, and for generating a redundant word line selection signal for selecting a respective redundant word line from said column redundant memory matrix; and output means, coupled to said column selector and to said column redundant selector, for selectively outputting an output from said column selector and said column redundant selector, whereby data stored in the electrically programmable memory cells of said column redundant memory matrix are read out in place of read only memory cells coupled to the defective data line of said memory matrix.

Claim 3

A semiconductor memory device according to claim 1, further comprising writing means, coupled to said column redundant memory matrix, for electrically writing data into the electrically programmable memory cells.

Claim 4

A semiconductor memory device according to claim 2, wherein each of the electrically programmable memory cells includes a control gate formed by a diffusion layer in a semiconductor body, and a floating gate including a conductive layer, said conductive layer partially overlapping a plan view area of said control gate through a thin insulating layer.

Claim 5

A semiconductor memory device according to claim 3, wherein each of the electrically programmable memory cells further includes a barrier layer which is formed above a principal surface of said semiconductor body and which has a portion for covering the entire floating gate corresponding thereto.

Claim 6

A semiconductor memory device according to claim 4, wherein said semiconductor body consists of a semiconductor substrate, wherein said diffusion layer consists of a first diffusion region, at the principal surface of said semiconductor substrate, and a high impurity concentration ohmic contact region formed therein, and wherein said ohmic contact region effects an electrical connection with a corresponding redundant word line.

Claim 7

A semiconductor memory device according to claim 2, further including a defective address storing circuit which stores defective column address signals and which includes a plurality of electrically programmable memory cells for storing the defective column address signals.

Claim 8

A semiconductor memory device according to claim 6, wherein each of the electrically programmable memory cells includes a control gate formed by a diffusion layer in a semiconductor body, and a floating gate including a conductive layer, said conductive layer partially overlapping a plan view area of said control gate through a thin insulating layer.

Claim 9

A semiconductor memory device according to claim 7, wherein each of the electrically programmable memory cells further includes a barrier layer which is formed above a principal surface of said semiconductor body and which has a portion for covering the entire floating gate corresponding thereto.

Claim 10

A semiconductor memory device according to claim 8, wherein said semiconductor body consists of a semiconductor substrate, wherein said diffusion layer consists of a first diffusion region, at the principal surface of said semiconductor substrate, and a high impurity concentration ohmic contact region formed therein, and wherein said ohmic contact region effects an electrical connection with a corresponding redundant word line.

Claim 11

A semiconductor memory device according to claim 6, wherein said column redundant memory matrix further includes redundant word lines and a plurality of electrically programmable memory cells which are coupled to the redundant data lines and the redundant word lines, and wherein one redundant word line is selected from said column redundant memory matrix in accordance with the redundant word line selection signal from said column detection means.

Claim 12

A semiconductor memory device according to claim 1, further comprising: a row redundant memory matrix including at least one redundant word line, a plurality of data lines and a plurality of electrically programmable memory cells which are coupled to said at Least one redundant word line and to the data lines thereof; a row redundant column decoder for generating a redundant selection signal in accordance with the column address signals; a row redundant column selector, coupled to the redundant data lines and to said row redundant column decoder, for selecting at least one of the redundant data lines in accordance with the column address signals; row detection means, for detecting coincidence of the row address signals to be supplied to said row decoder with a defective row address signal which indicates a defective word line in said memory matrix, and for generating a redundant word line selection signal for selecting a respective redundant word line from said row redundant memory matrix; and output means, coupled to said column selector and to said row redundant column selector, for selectively outputting an output from said column selector and said row redundant column selector, whereby data stored in the electrically programmmable memory cells of said row redundant memory matrix are read out in place of read only memory cells coupled to the defective word line of said memory matrix.

Claim 13

A semiconductor memory device according to claim 11, further including a defective address storing circuit which stores defective row address signals and which includes a plurality of electrically programmable memory cells for storing the defective row address signals.

Claim 14

A semiconductor memory device according to claim 12, wherein each of the electrically programmable memory cells of said row redundant memory matrix and of said defective address storing circuit includes a control gate formed by a diffusion layer in a semiconductor body, and a floating gate including a conductive layer, said conductive layer partially overlapping a plan view area of said control gate through a thin insulating layer.

Claim 15

A semiconductcr memory device according to claim 13, wherein each of the electrically programmable memory cells further includes a barrier layer which is formed above a principal surface of said semiconductor body and which has a portion for covering the entire floating gate corresponding thereto.

Claim 16

A semiconductor memory device according to claim 14, wherein said semiconductor body consists of a semiconductor substrate, wherein said diffusion layer consists of a first diffusion region, at the principal surface of said semiconductor substrate, and a high impurity concentration ohmic contact region formed therein, and wherein said ohmic contact region effects an electrical connection with a corresponding redundant word line.

Claim 17

A semiconductor memory device according to claim 8, further comprising: a row redundant memory matrix including at least one redundant word line, a plurality of data lines and a plurality of electrically programmable memory cells which are coupled to said at least one redundant word line and to the data lines thereof; a row redundant column decoder for generating a redundant selection signal in accordance with the column address signals; a row redundant column selector, coupled to the redundant data lines and to said row redundant column decoder, for selecting at least one of the redundant data lines in accordance with the row address signals; row detection means, for detecting coincidence of the row address signals to be supplied to said row decoder with a defective row address signal which indicates a defective word line in said memory matrix, and for generating a redundant word line selection signal for selecting a respective redundant word line from said row redundant memory matrix; and output means, coupled to said column selector and to said row redundant column selector, for selectively outputting an output from said column selector and said row redundant column selector, whereby data stored in the electrically programmable memory cells of said row redundant memory matrix are read out in place of read only memory cells coupled to the defective word line of said memory matrix.

Claim 18

A semiconductor memory device according to claim 16, further including a defective address storing circuit which stores defective row address signals and which includes a plurality of electrically programmable memory cells for storing the defective row address signals.

Claim 19

A semiconductor memory device according to claim 17, wherein each of the electrically programmable memory cells of said row redundant memory matrix and of said defective address storing circuit includes a control gate formed by a diffusion layer in a semiconductor body, and a floating gate including a conductive layer, said conductive layer partially overlapping a plan view area of said control gate through a thin insulating layer.

Claim 20

A semiconductor memory device according to claim 18, wherein each of the electrically programmable memory cells further includes a barrier layer which is formed above a principal surface of said semiconductor body and which has a portion for covering the entire floating gate corresponding thereto.

Claim 21

A semiconductor memory device according to claim 19, wherein said semiconductor body consists of a semiconductor substrate, wherein said diffusion layer consists of a first diffusion region, at the principal surface of said semiconductor substrate, and a high impurity concentration ohmic contact region formed therein, and wherein said ohmic contact region effects an electrical connection with a corresponding redundant word line.

Claim 22

A semiconductor memory device comprising: a memory matrix including a plurality of data lines, a plurality of word lines and a plurality of read only memory cells which are coupled to the data lines and to the word lines; a row decoder, coupled to the word lines, for selecting one of the word lines in accordance with row address signals; a column decoder for generating a selection signal in accordance with column address signals; a column selector, coupled to said column decoder and to the data lines, for selecting one of the data lines in accordance with the generated selection signal from said column decoder; a redundant memory matrix including a plurality of redundant word lines, a plurality of redundant data lines and a plurality of electrically programmable memory cells which are coupled to the redundant data lines and to said redundant word lines; a row redundant column decoder for generating a row redundant selection signal in accordance with the column address signals; a column redundant column decoder for generating a column redundant selection signal in accordance with the row address signals; a redundant column selector, coupled to the redundant data lines, to the row redundant column decoder and to the column redundant column decoder, for selecting at least one of the redundant data lines in accordance with one of the column address signals and the row address signals; detection means for detecting defects in said memory matrix, including means for detecting coincidence of the row address signals to be supplied to said row decoder with a defective row address signal which indicates a defective word line in said memory matrix and for generating a redundant word line selection signal for selecting one of the redundant word lines, and means for detecting coincidence of the column address signals to be supplied to said column decoder with a defective column address signal which indicates a defective data line in said memory matrix and for generating a redundant word line selection signal for selecting one of the redundant word lines; and output means, coupled to said column selector and to said redundant selector, for selectively outputting an output from said column selector and said redundant selector, whereby data stored in the electrically programmable memory cells of said redundant memory matrix are read out in place of read only memory cells coupled to one of the defective word line and the defective data line of said memory matrix.

Claim 23

A semiconductor memory device comprising: a memory matrix including a plurality of data lines, a plurality of word lines and a plurality of read only memory cells which are coupled to the data lines and to the word lines; a row decoder, coupled to the word lines, for selecting one of the word lines in accordance with row address signals; a column decoder for generating a selection signal in accordance with column address signals; a column selector, coupled to said column decoder and to the data lines, for selecting one of the data lines in accordance with the generated selection signal from said column decoder; a redundant memory matrix including a plurality of redundant word lines, a plurality of redundant data lines and a plurality of electrically programmable memory cells which are coupled to the redundant data lines and to said redundant word lines; a row redundant column decoder for generating a row redundant selection signal in accordance with the column address signals; a column redundant column decoder for generating a column redundant selection signal in accordance with the row address signals; a redundant column selector, coupled to the redundant data lines, to the row redundant column decoder and to the column redundant column decoder, for selecting at least one of the redundant data lines in accordance with one of the column address signals and the row address signals; detection means for detecting defects in said memory matrix, including means for detecting coincidence of the row address signals to be supplied to said row decoder with a defective row address signal which indicates a defective word line in said memory matrix and for generating a redundant word line selection signal for selecting one of the redundant word lines, and means for detecting coincidence of the column address signals to be supplied to said column decoder with a defective column address signal which indicates a defective data line in said memory matrix and for generating a redundant word line selection signal for selecting one of the redundant word lines; and output means, coupled to said column selector and to said redundant selector, for selectively outputting an output from said column selector and said redundant selector, whereby data stored in the electrically programmable memory cells of said redundant memory matrix are read out in place of read only memory cells coupled to one of the defective word line and the defective data line of said memory matrix.

Claim 24

A semiconductor memory device according to claim 21, wherein each of the electrically programmable memory cells includes a control gate formed by a diffusion layer in a semiconductor body and a floating gate including a conductive layer, said conductive layer partially overlapping a plan view area of said control gate through a thin insulating layer.

Claim 25

A semiconductor memory device according to claim 22, wherein each of the electrically programmable memory cells further includes a barrier layer which is formed above a principal surface of said semiconductor body and which has a portion for covering the entire floating gate corresponding thereto.

Claim 26

A semiconductor memory device according to claim 23, further comprising writing means, coupled to said redundant memory matrix, for electrically writing data into the electrically programmable memory cells.

Claim 27

A semiconductor memory device according to claim 23, further including a defective address storing circuit which stores defective row address signals and defective column address signals and which includes a plurality of electrically programmable memory cells.

Claim 28

A semiconductor memory device according to claim 25, further comprising writing means coupled to the defective address storing circuit for electrically writing data into the electrically programmable memory cells.

Claim 29

A semiconductor memory device according to claim 26, further comprising writing means coupled to the redundant memory matrix for electrically writing data into the electrically programmable memory cells.

Claim 30

A semiconductor memory device according to claim 27, wherein said semiconductor body consists of a semiconductor substrate, wherein said diffusion layer consists of a first diffusion region, at the principal surface of said semiconductor substrate, and a high impurity concentration ohmic contact region formed therein, and wherein said ohmic contact region effects an electrical connection with a corresponding redundant word line.