US5389859A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Display device including a correction circuit for correcting a position error, and correction circuit for use in such a display device
Assignee: US Philips Corp
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Filing: 1993-09-20
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Granted: 1995-02-14
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Expires: 2013-09-20
Abstract
Abstract A display device often includes a correction circuit for correcting a position error which is caused by the fact that the deflection signals are not (any longer) in conformity with the video signals to be displayed. This is caused, inter alia by the fact that the deflection coils and the display tube are not ideal. By providing the display device with a waveform generator generating a (line deflection) reference signal and by causing this reference signal to traverse the same "signal path" as the video signal, variations in the delay etc. can be corrected. Both the video signal and the reference signal are stored in a memory and read from the memory under the control of the correction circuit. Inputs of the correction circuit receive the (line deflection) reference signal delayed via the memory and a signal related to the (real) line deflection. With reference to these input signals, the correction circuit applies a (read) clock signal to the memory. As a result, deflection signals and video signals are always in conformity with each other.
Inventors
- 👤 Jeroen H. Stessen
- 👤 James J. A. McCormack
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 00:47
CPC Classifications
H; H04; H04N; H04N3/00; H04N3/10; H04N3/16; H04N3/22; H04N3/23; H04N3/233; H04N3/2335
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
245 words
A display device comprising a display tube for displaying video information, at least a line deflection coil and at least a field deflection coil, a deflection unit having a first output for applying a line deflection signal to the line deflection coil and a second output for applying a field deflection signal to the field deflection coil, a memory having an input for receiving and storing the video information under the control of a first clock signal and an output for reading the video information to be applied to the display tube under the control of a modulatable second clock signal, and a correction circuit for correcting a position error upon display of the video information on the display tube, with an input for receiving an input signal related to the line deflection current, said correction circuit comprising a modulatable clock generator for generating the second clock signal to be applied to the memory and an output for applying said second clock signal to the memory, characterized in that the display device includes a waveform generator for generating a reference signal related to the line deflection signal, and in that the memory has a section for storing the reference signal under the control of the first clock signal and for reading the reference signal modulated with the second clock signal from the memory under the control of the second clock signal, said modulated reference signal being applied as second input signal to the correction circuit.
Claim 2
Dependent Claim
245 words
A display device comprising a display tube for displaying video information, at least a line deflection coil and at least a field deflection coil, a deflection unit having a first output for applying a line deflection signal to the line deflection coil and a second output for applying a field deflection signal to the field deflection coil, a memory having an input for receiving and storing the video information under the control of a first clock signal and an output for reading the video information to be applied to the display tube under the control of a modulatable second clock signal, and a correction circuit for correcting a position error upon display of the video information on the display tube, with an input for receiving an input signal related to the line deflection current, said correction circuit comprising a modulatable clock generator for generating the second clock signal to be applied to the memory and an output for applying said second clock signal to the memory, characterized in that the display device includes a waveform generator for generating a reference signal related to the line deflection signal, and in that the memory has a section for storing the reference signal under the control of the first clock signal and for reading the reference signal modulated with the second clock signal from the memory under the control of the second clock signal, said modulated reference signal being applied as second input signal to the correction circuit.
Claim 3
Dependent Claim
33 words
A display device as claimed in claim 1, characterized in that the correction circuit is adapted to apply a control signal to the modulatable clock generator in dependence upon the two input signals.
Claim 4
Dependent Claim
40 words
A display device as claimed in claim 2, characterized in that the correction circuit comprises a differential amplifier having two inputs for receiving the two input signals and an output for applying the control signal to the modulatable clock generator.
Claim 5
Dependent Claim
65 words
A display device as claimed in claim 1, characterized in that the waveform generator is also adapted to generate the field deflection signal which is written into the memory under the control of the first clock signal via an extra input of the memory and, while being modulated with the second clock signal, is read from the memory and applied to the field deflection coil.
Claim 6
Dependent Claim
65 words
A display device as claimed in claim 2, characterized in that the waveform generator is also adapted to generate the field deflection signal which is written into the memory under the control of the first clock signal via an extra input of the memory and, while being modulated with the second clock signal, is read from the memory and applied to the field deflection coil.
Claim 7
Dependent Claim
65 words
A display device as claimed in claim 3, characterized in that the waveform generator is also adapted to generate the field deflection signal which is written into the memory under the control of the first clock signal via an extra input of the memory and, while being modulated with the second clock signal, is read from the memory and applied to the field deflection coil.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-13 | 1998-08-15 | 1999-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-13 | 2002-08-15 | 2003-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-13 | 2006-08-15 | 2007-02-14 | $7700.00 | Window Closed / Lapsed |