Patent US5546042A successfully refreshed from Google Patents.
Patent US5395772A successfully refreshed from Google Patents.
US5395772A
Expired / Lapsed
US
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SOI type MOS transistor device
Assignee: Sony Corp
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Filing: 1994-03-17
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Granted: 1995-03-07
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Expires: 2014-03-17
Abstract
Abstract An SOIMOS transistor device which comprises a substrate, an insulating film formed on the substrate, a source and a drain sandwiching a channel region therebetween and formed on the insulating film is described. The channel region has regions in contact with the source and the drain, respectively, and each region has a concentration of an impurity lower than those of the source and the drain, and a gate electrode is formed on the SOI layer. The regions are formed by diffusion of the impurity from the source and the drain in lateral directions, respectively, and extending beneath the gate electrode along the thickness of the source and the drain.
Inventors
- 👤 Yoshihiro Miyazawa
- 👤 Makoto Hashimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:40
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
177 words
A method for manufacturing a SOI MOS transistor device comprising the steps of: providing a substrate; forming an insulating film on a surface of said substrate; forming an SOI layer which has a thickness of 0.1 μm or less on said insulating film; forming a gate insulating film on a portion of said SOI layer; first ion implanting an n-type low concentration impurity into said SOI layer, using said gate electrode as a mask, to form a source region and a drain region; applying a thermal treatment to said device to form a lightly-doped source region and a lightly-doped drain region by side diffusion of said n-type low concentration impurity in said course region and said drain region, under the opposite side edges of said gate electrode, said lightly doped source region and said light-doped drain region disposed below and under the side edges of said gate electrode; and second ion implanting an n-type high concentration impurity into said SOI layer using said gate electrode as a mask to form said source region and said drain region.
Claim 2
Independent Claim
177 words
A method for manufacturing a SOI MOS transistor device comprising the steps of: providing a substrate; forming an insulating film on a surface of said substrate; forming an SOI layer which has a thickness of 0.1 μm or less on said insulating film; forming a gate insulating film on a portion of said SOI layer; first ion implanting an n-type low concentration impurity into said SOI layer, using said gate electrode as a mask, to form a source region and a drain region; applying a thermal treatment to said device to form a lightly-doped source region and a lightly-doped drain region by side diffusion of said n-type low concentration impurity in said course region and said drain region, under the opposite side edges of said gate electrode, said lightly doped source region and said light-doped drain region disposed below and under the side edges of said gate electrode; and second ion implanting an n-type high concentration impurity into said SOI layer using said gate electrode as a mask to form said source region and said drain region.
Claim 3
Independent Claim
207 words
A method for manufacturing a SOIMOS transistor device comprising the steps of: forming an SOI layer which has a thickness of 0.1 μm or less on a substrate; forming a gate electrode over a portion of said SOI layer; first implanting a low concentration impurity of a first type into said SOI layer using said gate electrode as a mask to form a source region, a drain region and a channel region, said channel region disposed below said portion of said SOI layer over which said gate electrode is formed; applying a thermal treatment to said device to produce a low concentration impurity of said first type source region and a low concentration impurity of said first type drain region, said low concentration impurity source region disposed under the side edge of said gate electrode between said channel region and said source region, and said low concentration impurity drain region disposed under the side edge of said gate electrode between said channel region and said drain region; and second implanting said SOI layer with a high concentration impurity of said first type using said gate electrode as a mask so as to increase the first type of impurity concentration in and form said source and drain regions.
Claim 4
Independent Claim
207 words
A method for manufacturing a SOIMOS transistor device comprising the steps of: forming an SOI layer which has a thickness of 0.1 μm or less on a substrate; forming a gate electrode over a portion of said SOI layer; first implanting a low concentration impurity of a first type into said SOI layer using said gate electrode as a mask to form a source region, a drain region and a channel region, said channel region disposed below said portion of said SOI layer over which said gate electrode is formed; applying a thermal treatment to said device to produce a low concentration impurity of said first type source region and a low concentration impurity of said first type drain region, said low concentration impurity source region disposed under the side edge of said gate electrode between said channel region and said source region, and said low concentration impurity drain region disposed under the side edge of said gate electrode between said channel region and said drain region; and second implanting said SOI layer with a high concentration impurity of said first type using said gate electrode as a mask so as to increase the first type of impurity concentration in and form said source and drain regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-06 | 1998-09-05 | 1999-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-06 | 2002-09-05 | 2003-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-06 | 2006-09-05 | 2007-03-07 | $7700.00 | Window Closed / Lapsed |