Single transistor flash electrically programmable memory cell in which a negative voltage is applied to the nonselected word line

Claim 2

An array of flash EEPROM memory cells wherein each memory cell is programmable by injecting electrons into its floating gate and wherein a negative voltage is applied to the nonselected word line of said array in a reading operation.

Claim 3

The array of flash EEPROM memory cells as set forth in claim 1, further comprising a word line decoding circuit comprising a first power supply terminal and a second power supply terminal, wherein a potential applied to said second power supply terminal in said reading operation is a negative voltage.

Claim 4

The array of flash EEPROM memory cells as set forth in claim 1, wherein the negative voltage is in a range of about -2 V to about -5 V.

Claim 5

The array of flash EEPROM memory cells as set forth in claim 1, wherein the negative voltage is about -3 V.

Claim 6

The flash EEPROM memory cell as set forth in claim 1, further comprising a word line decoding circuit comprising a level conversion circuit comprising: a pair of inverters whose input and output terminals are cross coupled to each other; and a transfer gate having a terminal coupled to an output of said word line decoding circuit and another terminal coupled to an input/output terminal of said level conversion circuit.

Claim 7

The array of flash EEPROM memory cells as set forth in claim 1, further comprising a CMOS inverter which comprises a p-channel MOS transistor and an n-channel transistor, wherein the source of the p-channel MOS transistor is connected to a terminal of a supply voltage V ROW P, the source of the n-channel MOS transistor is connected to the terminal of a supply voltage V ROW N, and the output of the CMOS inverter is connected to a word line of the memory cell.

Claim 8

The array of flash EEPROM memory cells as set forth in claim 6, wherein the n-channel transistor has a double well structure, wherein an n-type well is formed in a p-type substrate, and a p-type well is formed in the n-type well, and further a transistor is formed in the p-type well.

Claim 9

An array of flash EEPROM memory cells wherein each memory cell is programmable by injecting electrons into its floating gate and wherein a negative voltage is applied to the nonselected word line of said array in a reading operation, further comprising a word line decoding circuit comprising: a first power supply terminal and a second power supply terminal, wherein a potential applied to said first power supply terminal is greater than a potential applied to said second power supply terminal in said reading operation or in a writing operation and a potential applied to said second power supply terminal is greater than a potential applied to said first power supply terminal in an erasing operation; a level conversion circuit comprising a pair of inverters whose input and output terminals are cross coupled to each other; and a transfer gate having a terminal coupled to an output of said word line decoding circuit and another terminal coupled to an input/output terminal of said level conversion circuit.

Claim 10

An array of flash EEPROM memory cells wherein each memory cell is programmable by injecting electrons into its floating gate and wherein a negative voltage is applied to the nonselected word line of said array in a reading operation, further comprising a word line decoding circuit comprising: a first power supply terminal and a second power supply terminal, wherein a potential applied to said first power supply terminal is greater than a potential applied to said second power supply terminal in said reading operation or in a writing operation and a potential applied to said second power supply terminal is greater than a potential applied to said first power supply terminal in an erasing operation; a level conversion circuit comprising a pair of inverters whose input and output terminals are cross coupled to each other; and a transfer gate having a terminal coupled to an output of said word line decoding circuit and another terminal coupled to an input/output terminal of said level conversion circuit.

Claim 11

The array of flash EEPROM memory cells as set forth in claim 8, wherein the negative voltage is in a range of about -2 V to about -5 V.

Claim 12

The array of flash EEPROM memory cells as set forth in claim 8, wherein the negative voltage is about -3 V.

Claim 13

A flash EEPROM memory cell, comprising: a source region formed in a substrate and connected to a common line; a drain region formed in said substrate and connected to a bit line; a gate region located between said source region and said drain region; floating gate formed above said gate region and insulated from said gate region; a control gate formed above said floating gate and insulated from said floating gate, said control gate being connected to a word line; wherein during a reading operation, a negative voltage is applied to an unselected flash EEPROM memory cell on said word line.

Claim 14

A flash EEPROM memory cell, comprising: a source region formed in a substrate and connected to a common line; a drain region formed in said substrate and connected to a bit line; a gate region located between said source region and said drain region; floating gate formed above said gate region and insulated from said gate region; a control gate formed above said floating gate and insulated from said floating gate, said control gate being connected to a word line; wherein during a reading operation, a negative voltage is applied to an unselected flash EEPROM memory cell on said word line.

Claim 15

The flash EEPROM memory cell as set forth in claim 11, wherein the negative voltage is in a range of about -2 V to about -5 V.

Claim 16

The flash EEPROM memory cell as set forth in claim 11, wherein the negative voltage is about -3 V.

Claim 17

The flash EEPROM memory cell as set forth in claim 11, further comprising a CMOS inverter which comprises a p-channel MOS transistor and an n-channel transistor, wherein the source of the p-channel MOS transistor is connected to a terminal of a supply voltage V ROW p, the source of the n-channel MOS transistor is connected to the terminal of a supply voltage V ROW N, and the output of the CMOS inverter is connected to a word line of the memory cell.

Claim 18

The flash EEPROM memory cell as set forth in claim 14, wherein the n-channel transistor has a double well structure, wherein an n-type well is formed in a p-type substrate, and a p-type well is formed in the n-type well, and further a transistor is formed in the p-type well.

Claim 19

The flash EEPROM memory cell as set forth in claim 11, wherein said EEPROM memory cell is programmed by injecting electrons into said gate region.

Claim 20

The flash EEPROM memory cell as set forth in claim 11, further comprising a work line decoding circuit comprising a first power supply terminal and a second power supply terminal, wherein a potential applied to said second power supply terminal in said reading operation is a negative voltage.