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US5398207A
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US
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MOS random access memory device with an internal voltage-down converting transistor
Assignee: Toshiba Corp
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Filing: 1993-05-28
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Granted: 1995-03-14
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Expires: 2013-05-28
Abstract
Abstract A MOS dynamic random access memory device has a memory cell array section formed on a semiconductor substrate, including memory cells each having a data storage capacitor and a transfer-gate transistor. Parallel bit lines are associated with the memory cell array section. Parallel word lines extend transverse to the bit lines, including a word line connected to the transfer-gate transistor. A booster circuit is arranged to provide a potentially raised voltage which is higher than a power supply voltage. A sense amplifier circuit is connected with a corresponding bit line pair of the word lines. A word-line driver circuit has an input connected to the booster circuit and an output connected to the word line. A bit-line restoring circuit is connected to the sense amplifier circuit. The restoring circuit includes a voltage-down converting metal oxide semiconductor field effect transistor having an insulated gate connected to the booster circuit, a drain coupled to the power supply voltage, and a source at which a potentially decreased voltage appears to be lower than the power supply voltage. The voltage-down converting transistor is same in channel conductivity type as the transfer-gate transistor.
Inventors
- 👤 Kenji Tsuchida
- 👤 Takashi Ohsawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:42
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C11/408; G11C11/4085; G11C11/409; G11C11/4091; G11C11/4094
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
244 words
A semiconductor memory device comprising: a semiconductor substrate; an array of rows and columns of memory cells formed on said semiconductor substrate, each of said memory cells including a transistor and a capacitor; word lines coupled to said rows of memory cells; bit lines coupled to said columns of memory cells; a word-line driver circuit coupled to said word lines; restore circuit means coupled to said bit lines for restoring a selected one of said bit lines, associated with a presently selected one of said memory cells; and first voltage generator means coupled to a power supply voltage, for generating a first internal voltage which is greater in potential than said power supply voltage, said first internal voltage being applied to a control electrode of said transistor, wherein said restore circuit means includes second voltage generator means coupled to said power supply voltage, for generating a second internal voltage which is lower in potential than said power supply voltage, and means for causing said second internal voltage to be supplied to said bit lines as a restoring voltage, said second voltage generator means essentially consisting of a transistor having substantially the same threshold voltage as that of said transistor of each memory cell, and said transistor of said second voltage generator means having a first current carrying electrode supplied with said power supply voltage, a second current-carrying electrode coupled to said bit lines, and a control electrode coupled to said first voltage generator means.
Claim 2
Dependent Claim
244 words
A semiconductor memory device comprising: a semiconductor substrate; an array of rows and columns of memory cells formed on said semiconductor substrate, each of said memory cells including a transistor and a capacitor; word lines coupled to said rows of memory cells; bit lines coupled to said columns of memory cells; a word-line driver circuit coupled to said word lines; restore circuit means coupled to said bit lines for restoring a selected one of said bit lines, associated with a presently selected one of said memory cells; and first voltage generator means coupled to a power supply voltage, for generating a first internal voltage which is greater in potential than said power supply voltage, said first internal voltage being applied to a control electrode of said transistor, wherein said restore circuit means includes second voltage generator means coupled to said power supply voltage, for generating a second internal voltage which is lower in potential than said power supply voltage, and means for causing said second internal voltage to be supplied to said bit lines as a restoring voltage, said second voltage generator means essentially consisting of a transistor having substantially the same threshold voltage as that of said transistor of each memory cell, and said transistor of said second voltage generator means having a first current carrying electrode supplied with said power supply voltage, a second current-carrying electrode coupled to said bit lines, and a control electrode coupled to said first voltage generator means.
Claim 3
Dependent Claim
35 words
The semiconductor memory device according to claim 1, wherein said transistor of said second voltage generator means includes a metal insulator semiconductor transistor having an insulated gate electrode coupled to said first voltage generator means.
Claim 4
Dependent Claim
26 words
The semiconductor memory device according to claim 2, wherein said first voltage generator means and said second voltage generator means are arranged on said semiconductor substrate.
Claim 5
Dependent Claim
25 words
The semiconductor memory device according to claim 3, wherein said metal insulator semiconductor transistor is included in said semiconductor restore circuit means on said substrate.
Claim 6
Dependent Claim
30 words
The semiconductor memory device according to claim 3, wherein said metal insulator semiconductor transistor includes a metal oxide semiconductor field effect transistor or MOSFET of a chosen channel conductivity type.
Claim 7
Dependent Claim
29 words
The semiconductor memory device according to claim 3, wherein said first voltage generator means includes a booster circuit for generating a potentially increased voltage as said first internal voltage.
Claim 8
Dependent Claim
78 words
The semiconductor memory device according to claim 6, wherein said booster circuit includes: an operational amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal; an oscillator having an input terminal coupled to said output terminal of said operational amplifier, and an output terminal; and a charge-pump circuit having an input terminal coupled to said output terminal of said oscillator and an output terminal coupled to said inverting input terminal of said operational amplifier.
Claim 9
Dependent Claim
30 words
The semiconductor memory device according to claim 2, further comprising: a voltage-down converter circuit coupled to a peripheral circuit associated with said array of rows and columns of memory cells.
Claim 10
Dependent Claim
19 words
The semiconductor memory device according to claim 2, wherein said restore circuit means includes a constant current supply circuit.
Claim 11
Dependent Claim
66 words
The semiconductor memory device according to claim 9, wherein said constant current supply circuit includes: a differential amplifier having a first input terminal supplied with a reference voltage, a second input terminal, and an output terminal; and a transistor having a gate electrode coupled to said output terminal of said differential amplifier, and a current-carrying electrode coupled to said second input terminal of said differential amplifier.
Claim 12
Dependent Claim
157 words
A dynamic random access memory comprising: a semiconductor substrate; a memory cell array section including a plurality of memory cells which have data storage elements and transfer-gate transistors respectively; parallel bit lines associated with said memory cell array section; parallel word lines formed transverse to said bit lines and connected to said transfer-gate transistors of said memory cells; a word-line driver circuit connected to said word lines; a restoring circuit connected to said bit lines; first means for providing said word-line driver circuit with a first voltage which is potentially higher than a power supply voltage externally supplied to said dynamic random access memory; and second means, connected to said restoring circuit, for providing said restoring circuit with a second voltage which is potentially lower than said power supply voltage, said second means including a transistor having substantially the same threshold voltage as that of said transfer-gate transistors and a gate electrode coupled to said first means.
Claim 13
Dependent Claim
157 words
A dynamic random access memory comprising: a semiconductor substrate; a memory cell array section including a plurality of memory cells which have data storage elements and transfer-gate transistors respectively; parallel bit lines associated with said memory cell array section; parallel word lines formed transverse to said bit lines and connected to said transfer-gate transistors of said memory cells; a word-line driver circuit connected to said word lines; a restoring circuit connected to said bit lines; first means for providing said word-line driver circuit with a first voltage which is potentially higher than a power supply voltage externally supplied to said dynamic random access memory; and second means, connected to said restoring circuit, for providing said restoring circuit with a second voltage which is potentially lower than said power supply voltage, said second means including a transistor having substantially the same threshold voltage as that of said transfer-gate transistors and a gate electrode coupled to said first means.
Claim 14
Dependent Claim
29 words
The dynamic random access memory according to claim 11, wherein said transistor of said second means does not have a greater threshold voltage than that of said transfer-gate transistors.
Claim 15
Dependent Claim
30 words
The dynamic random access memory according to claim 12, wherein said transistor of said second means has a threshold voltage which is substantially equivalent to that of said transfer-gate transistors.
Claim 16
Dependent Claim
35 words
The dynamic random access memory according to claim 11, wherein said first means comprises a circuit arranged on said semiconductor substrate for internally generating a potentially increased voltage with respect to said power supply voltage.
Claim 17
Dependent Claim
45 words
The dynamic random access memory according to claim 14, wherein said transistor has a drain electrode supplied with said power supply voltage and a source electrode coupled to said restoring circuit, said gate electrode of said transistor being also coupled to said word-line driver circuit.
Claim 18
Dependent Claim
72 words
The dynamic random access memory according to claim 15, further comprising: an input stage circuit section; a peripheral circuit section having an input terminal connected to said input stage circuit section and an output terminal connected to said memory cell array section; and a voltage-down converter circuit having an input terminal supplied with said power supply voltage and an output terminal connected to said input-stage circuit section and said peripheral circuit section.
Claim 19
Dependent Claim
24 words
The dynamic random access memory according to claim 13, wherein said transistor of said second means and said transfer-gate transistors include field effect transistors.
Claim 20
Dependent Claim
26 words
The dynamic random access memory according to claim 17, wherein said field effect transistors are metal oxide semiconductor field effect transistors of N type channel conductivity.
Claim 21
Dependent Claim
211 words
A dynamic random access memory system comprising: a memory cell array section including a plurality of memory cells each of which has a data storage element and a transfer-gate transistor with a control gate electrode; parallel bit lines associated with said memory cell array section, said parallel bit lines including a bit line pair; parallel word lines formed transverse to said parallel bit lines, including a word line connected to said control gate electrode of said transfer-gate transistor; booster circuit means supplied with a power supply voltage, for providing a potentially raised voltage which is higher than said power supply voltage; a sense amplifier circuit associated with said bit line pair; a word-line driver circuit having an input terminal connected to said booster circuit means and an output terminal connected to said word line; and a restoring circuit connected to said sense amplifier circuit, said restoring circuit including a voltage-down converting metal oxide semiconductor field effect transistor having an insulated gate electrode connected to said booster circuit means, a drain electrode supplied with said power supply voltage, and a source electrode whereat a potentially decreased voltage appears which is lower than said power supply voltage, said voltage-down converting transistor having substantially the same threshold voltage as that of said transfer-gate transistor.
Claim 22
Dependent Claim
211 words
A dynamic random access memory system comprising: a memory cell array section including a plurality of memory cells each of which has a data storage element and a transfer-gate transistor with a control gate electrode; parallel bit lines associated with said memory cell array section, said parallel bit lines including a bit line pair; parallel word lines formed transverse to said parallel bit lines, including a word line connected to said control gate electrode of said transfer-gate transistor; booster circuit means supplied with a power supply voltage, for providing a potentially raised voltage which is higher than said power supply voltage; a sense amplifier circuit associated with said bit line pair; a word-line driver circuit having an input terminal connected to said booster circuit means and an output terminal connected to said word line; and a restoring circuit connected to said sense amplifier circuit, said restoring circuit including a voltage-down converting metal oxide semiconductor field effect transistor having an insulated gate electrode connected to said booster circuit means, a drain electrode supplied with said power supply voltage, and a source electrode whereat a potentially decreased voltage appears which is lower than said power supply voltage, said voltage-down converting transistor having substantially the same threshold voltage as that of said transfer-gate transistor.
Claim 23
Dependent Claim
43 words
The dynamic random access memory system according to claim 19, wherein said restoring circuit includes a sense-amplifier driver circuit having an input terminal connected to said source electrode of said voltage-down converting transistor and an output terminal connected to said sense amplifier circuit.
Claim 24
Dependent Claim
28 words
The dynamic random access memory system according to claim 20, wherein said voltage-down converting transistor does not have a greater threshold voltage than that of said transfer-gate transistor.
Claim 25
Dependent Claim
26 words
The dynamic random access memory system according to claim 21, wherein said voltage-down converting transistor and said transfer-gate transistor are of an N channel conductivity type.
Claim 26
Dependent Claim
27 words
The dynamic random access memory system according to claim 22, wherein said voltage-down converting transistor has a threshold voltage substantially equal to that of said transfer-gate transistor.
Claim 27
Dependent Claim
73 words
The dynamic random access memory system according to claim 23, further comprising: an input stage circuit section; a peripheral circuit section having an input terminal connected to said input stage circuit section and an output terminal connected to said memory cell array section; and a voltage-down converter circuit having an input terminal supplied with said power supply voltage and an output terminal connected to said input-stage circuit section and said peripheral circuit section.
Claim 28
Dependent Claim
66 words
The dynamic random access memory system according to claim 24, wherein said restoring circuit comprises: a second metal oxide semiconductor field effect transistor connected between said sense amplifier circuit and said source electrode of said voltage-down converting transistor; and charge current controller means connected to said second transistor, for decreasing a peak of a restoring current supplied through said second transistor to said sense amplifier circuit.
Claim 29
Dependent Claim
20 words
The dynamic random access memory system according to claim 25, wherein said second transistor has an N channel conductivity type.
Claim 30
Dependent Claim
34 words
The dynamic random access memory system according to claim 25, wherein said charge current controller means comprises: a constant current supplying circuit including a differential amplifier, a reference resistor, and a voltage-to-current converting transistor.
References Cited (Backward Citations)
US5103113A
Cited
US5249155A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-13 | 1998-09-12 | 1999-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-13 | 2002-09-12 | 2003-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-13 | 2006-09-12 | 2007-03-14 | $7700.00 | Window Closed / Lapsed |