Device for the 3D encapsulation of semiconductor chips

Claim 3

A device according to claim 1, wherein said face of the stack located on the fourth side of the chips does not have conductors, said stack further comprising stack pads formed on one or more of its faces with the exception of said face, said stack pads being designed for the connection of the stack with external circuits, said connections further linking at least certain of the conductors with the stack pads.

Claim 4

A device according to claim 1, wherein said face of the stack which is located on the fourth face of the chips is connected to heat dissipation means.

Claim 5

A device according to claim 1 wherein the conductors are wires or strips.

Claim 6

A device according to claim 1, wherein said insulating film of said connection means has a surface area smaller than the surface area of said chip, and is positioned on the face of the chip that bears the pads.

Claim 7

A device to claim 1, wherein said insulating film of said connection means has dimensions greater than the dimensions of the chip and wherein it is positioned on the rear face of the chip, which does not bear pads.

Claim 8

A device according to claim 1, wherein a fourth side of the chip is flush with the face of the stack.

Claim 9

A device according to claim 1, wherein said connections comprise a conductive layer covering substantially all the faces of the stack, said conductive layer being etched so as to form said connections.

Claim 10

A device according to claim 1, wherein said connections comprise grooves made in the stack and a conductive layer positioned in the grooves.

Claim 11

A device according to claim 1, wherein said chips and connection means are embedded in said insulating material.

Claim 12

A device according to claim 2, wherein said insulating material is a resin.

Claim 13

A semiconductor stack comprising: (a) a plurality of semiconductor chips each having two major faces and four side faces, a plurality of connection pads distributed on one major face near a periphery of said face close to four sides of said chip, said chip being positioned with the major faces parallel to each other; (b) a plurality of first conductors extending from the pads on three of said peripherals outward from said chips and substantially parallel to said major faces; (c) a plurality of central frames of dielectric material, one for each of said chips, and having a plurality of electrically conductive tracks thereon, each of said frames being positioned adjacent to one of said chips, each track having one end near said fourth side of said chip and the other end near one of the three other sides; (d) a plurality of electrical connections extending between the pads on the fourth of said peripheries of said chips to said one end of said electrically conductive tracks; (e) a plurality of second conductors extending from said other end of said tracks outward from said chips and frames and substantially parallel to said major surfaces; (f) an insulating material between said chips and bonding said chips, frames, and conductors into a single stack with the conductors extending to three surfaces of said stack which correspond to said three sides of said chips.

Claim 14

A semiconductor stack comprising: (a) a plurality of semiconductor chips each having two major faces and four side faces, a plurality of connection pads distributed on one major face near a periphery of said face close to four sides of said chip, said chip being positioned with the major faces parallel to each other; (b) a plurality of first conductors extending from the pads on three of said peripherals outward from said chips and substantially parallel to said major faces; (c) a plurality of central frames of dielectric material, one for each of said chips, and having a plurality of electrically conductive tracks thereon, each of said frames being positioned adjacent to one of said chips, each track having one end near said fourth side of said chip and the other end near one of the three other sides; (d) a plurality of electrical connections extending between the pads on the fourth of said peripheries of said chips to said one end of said electrically conductive tracks; (e) a plurality of second conductors extending from said other end of said tracks outward from said chips and frames and substantially parallel to said major surfaces; (f) an insulating material between said chips and bonding said chips, frames, and conductors into a single stack with the conductors extending to three surfaces of said stack which correspond to said three sides of said chips.

Claim 15

A stack according to claim 12, further comprising a third plurality of conductors on said three sides of said stack connected to the first and second conductors at said surfaces.

Claim 16

A stack according to claim 12, further comprising a heat sink connected to a fourth surface of said stack which comprises said fourth side surface of said chips, and said heat sink being in good thermal contact with said fourth side of said chips.

Claim 17

A stack according to claim 12, wherein said fourth side surface of said chips is at a fourth surface of said stack.

Claim 18

A stack according to claim 15, further comprising means for conducting heat connected to said fourth side of said stack.

Claim 19

A stack according to claim 12, further comprising a plurality of thermally conductive layers, each of said layers being positioned adjacent said frames on a face of the frame opposite the chip to form a sandwich of chip-frame-layer, and with the sandwiches separated by said insulating material.

Claim 20

A stack according to claim 17, wherein said thermally conductive layers extend with edges to a fourth side of said stack, and said fourth side corresponds to a fourth side of said chips.