Patent US5401678A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5401678A Expired / Lapsed US ⏱️ 0.0 years remaining

Transistor and method for fabricating the same

Assignee: SK Hynix Inc
•
Filing: 1993-12-02
•
Granted: 1995-03-28
•
Expires: 2013-12-02
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An LDD transistor, preventive of the weakening of source/drain junction breakdown voltage and the increase of junction leakage current, and a method for the fabrication of the same. The LDD transistor is comprised of: a field oxide film formed on a predetermined portion of a semiconductor having a low density ion-implanted region therein, the field oxide film having a damaged portion; a gate electrode formed over the field oxide film; an insulating film formed over the gate electrode; a gate polyoxide film resulting from the oxidation of the side wall of the gate electrode; a spacer insulating film formed at the side wall provided by the gate polyoxide film and the insulating film atop the gate polyoxide film; a pad polysilicon film deposited over the insulating film, spacer oxide film, the low density ion-implanted region and the field oxide film; and a high density ion-implanted region formed below the pad polysilicon film, being confined within the low density ion-implanted region.

Inventors

  • 👤 Jae G. Jeong
  • 👤 Youn J. Kim

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 08:58
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/0184; H10D84/0191

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 200 words
In a method for fabricating a transistor wherein a semiconductor substrate is sectioned into an operational region and a device separation region by the formation of a field oxide with a bird's beak and has in said operational region a low density ion-implanted region which a high density ion-implanted region is confined within, so as not to contact said high density ion-implanted region with said semiconductor substrate when forming a source or drain region, the improvement which comprises the steps of: forming a gate electrode on said field oxide film said gate electrode being insulated by an insulating film formed thereon and a gate polyoxide film resulting from the oxidation of its side wall; forming a spacer insulating film at the side wall provided by said insulating film and said gate polyoxide film; depositing a pad polysilicon film entirely over the resulting structure so as to implant high density impurity ions in said pad polysilicon film; etching said pad polysilicon film so as to leave said pad polysilicon film atop said operational region and said spacer insulating film; and applying a thermal process to form one of said source region and said drain region within said low density ion-implanted region.
Claim 2
Dependent Claim 200 words
In a method for fabricating a transistor wherein a semiconductor substrate is sectioned into an operational region and a device separation region by the formation of a field oxide with a bird's beak and has in said operational region a low density ion-implanted region which a high density ion-implanted region is confined within, so as not to contact said high density ion-implanted region with said semiconductor substrate when forming a source or drain region, the improvement which comprises the steps of: forming a gate electrode on said field oxide film said gate electrode being insulated by an insulating film formed thereon and a gate polyoxide film resulting from the oxidation of its side wall; forming a spacer insulating film at the side wall provided by said insulating film and said gate polyoxide film; depositing a pad polysilicon film entirely over the resulting structure so as to implant high density impurity ions in said pad polysilicon film; etching said pad polysilicon film so as to leave said pad polysilicon film atop said operational region and said spacer insulating film; and applying a thermal process to form one of said source region and said drain region within said low density ion-implanted region.
Claim 3
Dependent Claim 50 words
A method according to claim 1, further comprising the steps of: forming an interlayer insulating film over said pad polysilicon film; and etching said pad polysilicon film to form a contact hole, through which said high density ion-implanted region formed in said low density ion-implanted region can be electrically connected.
Claim 4
Dependent Claim 27 words
A method according to claim 1, wherein said low density ion-implanted region has an impurity ion concentration of approximately 1×10 17 to 1×10 19 atoms/cm 3 .
Claim 5
Dependent Claim 27 words
A method according to claim 1, wherein said high density ion-implanted region has an impurity ion concentration of not less than approximately 1×10 20 atoms/cm 3 .

References Cited (Backward Citations)

US5026657A Cited
US5082796A Cited
US5073510A Cited
US5196357A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-03-27 1998-09-26 1999-03-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-03-27 2002-09-26 2003-03-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-03-27 2006-09-26 2007-03-28 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag