US5404455A
Expired / Lapsed
US
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Time division multiplexer chip for supporting alternating communication between a pair of RAMs and two different interfaces
Assignee: Dictaphone Corp
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Filing: 1991-12-31
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Granted: 1995-04-04
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Expires: 2011-12-31
Abstract
Abstract A time division multiplexer (TDM) chip having particular application in a digital voice processing system wherein voice processing functions are run in software. The TDM chip has a pair of RAMs which are in communication with a bus and at least one interface that provides communication with other devices. An bank switch controls the RAMs so that their communication with the bus and the interface alternates, i.e. while the first RAM is in communication with the interface the other RAM is in communication with the bus. After a determined period the communications are reversed. This scheme provides faster processing and more efficient use of the components. Including is a provision for allowing multiple interfaces to communicate with the RAM alternatively in a time shared manner.
Inventors
- 👤 Daniel F. Daly
- 👤 John J. Dwyer
- 👤 Salvatore J. Morlando
- 👤 Mark Sekas
- 👤 Shamla V. Sharma
- 👤 Judith Dixon-Otton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:25
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0421; H04M; H04M3/00; H04M3/42; H04M3/487; H04M3/50; H04M3/53; H04M3/533
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
202 words
A time division multiplex chip, comprising: at least one first interface, a pair of RAMs in alternate communication with said at least one first interface, wherein said at least one first interface is a plurality of interfaces and further comprising an interrupt unit in communication with said plurality of first interfaces for controlling which of said first interfaces is to be in communication with one of said RAMS, a second interface in alternate communication with said pair of RAMs, an address generator in alternate communication with said pair of RAMs, a bank switch unit in communication with said pair of RAMs for switching communication of each RAM of said pair of RAMs alternately with said at least one first interface, said address generator and said second interface, a clock in communication with said bank switch unit for providing a frame synch clock signal to said bank switch unit whereby upon each frame boundary said pair of RAMs will be switched; a failure detector in communication with said second interface to determine if data sent from said second interface is data received from one of said RAMs; and a clock failure detector with said clock for determining if said clock has a failure.
Claim 2
Dependent Claim
202 words
A time division multiplex chip, comprising: at least one first interface, a pair of RAMs in alternate communication with said at least one first interface, wherein said at least one first interface is a plurality of interfaces and further comprising an interrupt unit in communication with said plurality of first interfaces for controlling which of said first interfaces is to be in communication with one of said RAMS, a second interface in alternate communication with said pair of RAMs, an address generator in alternate communication with said pair of RAMs, a bank switch unit in communication with said pair of RAMs for switching communication of each RAM of said pair of RAMs alternately with said at least one first interface, said address generator and said second interface, a clock in communication with said bank switch unit for providing a frame synch clock signal to said bank switch unit whereby upon each frame boundary said pair of RAMs will be switched; a failure detector in communication with said second interface to determine if data sent from said second interface is data received from one of said RAMs; and a clock failure detector with said clock for determining if said clock has a failure.
Claim 3
Dependent Claim
204 words
A time division multiplex chip for use in a voice processing system comprising: a pair of first interfaces, a pair of RAMs in alternate individual, selective communication with said pair of first interfaces, an arbitration unit in communication with said pair of first interfaces to control which of said interfaces is to communicate with RAMs, a second interface in alternate individual selective communication with said pair of RAMs, a bank switching unit in communication with said pair of RAMs for switching communication of each of said RAMs between said pair of first interfaces and second interface, and a clock in communication with said arbitration unit and with said bank switching unit for providing a frame synch clock signal to said bank switching unit whereby upon each frame boundary said pair of RAMs switch communication between said first pair of interface and said second interface and a second pair of first interfaces each of which is in individual selective communication with said pair of RAMs, a second arbitration unit in communication with said clock and with said second pair of first interfaces for controlling which of said second pair of first interfaces is to be in communication with one or the other of said RAMs.
Claim 4
Dependent Claim
204 words
A time division multiplex chip for use in a voice processing system comprising: a pair of first interfaces, a pair of RAMs in alternate individual, selective communication with said pair of first interfaces, an arbitration unit in communication with said pair of first interfaces to control which of said interfaces is to communicate with RAMs, a second interface in alternate individual selective communication with said pair of RAMs, a bank switching unit in communication with said pair of RAMs for switching communication of each of said RAMs between said pair of first interfaces and second interface, and a clock in communication with said arbitration unit and with said bank switching unit for providing a frame synch clock signal to said bank switching unit whereby upon each frame boundary said pair of RAMs switch communication between said first pair of interface and said second interface and a second pair of first interfaces each of which is in individual selective communication with said pair of RAMs, a second arbitration unit in communication with said clock and with said second pair of first interfaces for controlling which of said second pair of first interfaces is to be in communication with one or the other of said RAMs.
Claim 5
Dependent Claim
26 words
The time division multiplexer chip of claim 2 further including a time slot address generator in communication with said pair of RAMs and with said clock.
Claim 6
Dependent Claim
21 words
The time division multiplexer chip of claim 2 further comprising an interrupt unit in communication with said time slot address generator.
Claim 7
Dependent Claim
42 words
The time division multiplexor chip of claim 4 further comprising a failure detector in communication with said second interface to determine if data sent from said second interface is the same data received by said second interface from one of said RAMs.
Claim 8
Independent Claim
232 words
A method of processing voice data, the steps comprising: a. transmitting first voice data to a first interface, b. connecting the first interface with a first RAM, c. transferring said first voice data from said first interface to said first RAM, includes transferring said first voice data from a time division multiplexer bus to said first interface d. transmitting second voice data to a second interface, e. connecting said second interface to a second RAM, f. transferring said second voice data from said second interface to said second RAM includes transferring second voice data from a signal processor to said second interface, g. discontinuing connection between said first interface and said first RAM, h. discontinuing connection between said second interface and said second RAM, I. connecting said first interface to said second RAM, j. transferring second voice data from said second RAM to said first interface, k. outputting second voice data from said first interface, I. transmitting third voice data to said first interface, m. connecting said second interface with said first RAM, n. transferring first voice data from said first RAM to said second interface, o. outputting first voice data from said second interface, and p. transmitting fourth voice data to said second interface, wherein a failure detector in communication with said second interface to determine if data sent from said second interface is data received from one of said RAMs.
Claim 9
Independent Claim
232 words
A method of processing voice data, the steps comprising: a. transmitting first voice data to a first interface, b. connecting the first interface with a first RAM, c. transferring said first voice data from said first interface to said first RAM, includes transferring said first voice data from a time division multiplexer bus to said first interface d. transmitting second voice data to a second interface, e. connecting said second interface to a second RAM, f. transferring said second voice data from said second interface to said second RAM includes transferring second voice data from a signal processor to said second interface, g. discontinuing connection between said first interface and said first RAM, h. discontinuing connection between said second interface and said second RAM, I. connecting said first interface to said second RAM, j. transferring second voice data from said second RAM to said first interface, k. outputting second voice data from said first interface, I. transmitting third voice data to said first interface, m. connecting said second interface with said first RAM, n. transferring first voice data from said first RAM to said second interface, o. outputting first voice data from said second interface, and p. transmitting fourth voice data to said second interface, wherein a failure detector in communication with said second interface to determine if data sent from said second interface is data received from one of said RAMs.
Claim 10
Dependent Claim
34 words
The method of claim 6 further including the step of determining if the data output from said first interface is the same as the data received by said first interface from said second RAM.
Claim 11
Dependent Claim
50 words
The method of claim 6 wherein the step outputting second voice data from said first interface includes transferring said second voice data to a time division multiplexer bus and the step of outputting first voice data from said second interface includes outputting said first voice data to a signal processor.
References Cited (Backward Citations)
US3772657A
Cited
US4298954A
Cited
US4442485A
Cited
US4549047A
Cited
US4602331A
Cited
US4799144A
Cited
US4785473A
Cited
US5163132A
Cited
EP0323248A2
Cited
EP0437515A1
Cited
US5031146A
Cited
US5130975A
Cited
EP0554626A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-03 | 1998-10-03 | 1999-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-03 | 2002-10-03 | 2003-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-03 | 2006-10-03 | 2007-04-04 | $7700.00 | Window Closed / Lapsed |