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US5405789A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing a semiconductor device whereby a laterally bounded semiconductor zone is formed in a semiconductor body in a self-aligning manner

Assignee: US Philips Corp
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Filing: 1993-10-22
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Granted: 1995-04-11
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Expires: 2013-10-22
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Abstract

Abstract A method of manufacturing a semiconductor device with a semiconductor element which includes a semiconductor zone (19) situated below an electrode (18) and adjoining a surface (5) of a semiconductor body (1), which semiconductor zone substantially does not project outside the electrode (18) in lateral direction. The electrode (18) is here formed on the surface (5) of the semiconductor body (1), after which semiconductor material adjoining the surface (5) and not covered by the electrode (18) is removed by an etching treatment, whereby the position of the semiconductor zone (19) below the electrode (18) is defined. Before the electrode (18) is formed, a surface zone (16) adjoining the surface (5) is formed in the semiconductor body (1) with a depth and a doping such as are desired for the semiconductor zone (19) to be formed below the electrode (18), after which the electrode (18) is formed on this surface zone and, during the etching treatment, the portion of the surface zone (16) not covered by the electrode (18) is etched away through its entire thickness. Conducting materials such as aluminium or aluminium alloys may be used for the electrode (18), i.e. materials which are not resistant to temperatures necessary for forming semiconductor zones through diffusion.

Inventors

  • 👤 Ronald Dekker
  • 👤 Henricus G. R. Maas
  • 👤 Armand Pruijmboom
  • 👤 Wilhelmus T. A. J. van den Einden

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 06:53
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D10/00; H10D10/01; H10D10/051; H10D10/056; H10D10/058; H10D30/00; H10D30/01; H10D30/012; H10D64/00; H10D64/01; H10D64/011; H10D84/02; H10D84/03; H10D84/038

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 217 words
A method of manufacturing a semiconductor device with a semiconductor element which comprises a semiconductor zone which is situated below an electrode, adjoins a surface of a semiconductor body, and substantially does not extend laterally outside the electrode, in which method an electrode is formed on the surface of the semiconductor body, after which semiconductor material adjoining the surface and not covered by the electrode is removed by an etching treatment, whereby the position of the semiconductor zone below the electrode is defined, characterized in that, before the electrode (18) is formed, a surface zone (16) adjoining the surface (5) is formed in the semiconductor body (1) through deposition of a base layer (12) of doped semiconductor material on the surface (5) and through diffusion of dopant into the semiconductor body (1) from this base layer (12), with a depth and a doping as desired for the semiconductor zone (19) to be formed below the electrode (18), after which a top layer (13, 14) comprising metal is deposited on the doped base layer (12) and the electrode (18) is formed in the base layer (12) and the top layer (13, 14), and the portion of the surface zone (16) not covered by the electrode (18) is then etched away throughout its entire thickness during the etching treatment.
Claim 2
Independent Claim 217 words
A method of manufacturing a semiconductor device with a semiconductor element which comprises a semiconductor zone which is situated below an electrode, adjoins a surface of a semiconductor body, and substantially does not extend laterally outside the electrode, in which method an electrode is formed on the surface of the semiconductor body, after which semiconductor material adjoining the surface and not covered by the electrode is removed by an etching treatment, whereby the position of the semiconductor zone below the electrode is defined, characterized in that, before the electrode (18) is formed, a surface zone (16) adjoining the surface (5) is formed in the semiconductor body (1) through deposition of a base layer (12) of doped semiconductor material on the surface (5) and through diffusion of dopant into the semiconductor body (1) from this base layer (12), with a depth and a doping as desired for the semiconductor zone (19) to be formed below the electrode (18), after which a top layer (13, 14) comprising metal is deposited on the doped base layer (12) and the electrode (18) is formed in the base layer (12) and the top layer (13, 14), and the portion of the surface zone (16) not covered by the electrode (18) is then etched away throughout its entire thickness during the etching treatment.
Claim 3
Dependent Claim 57 words
A method as claimed in claim 1, characterized in that a base layer (12) of doped polycrystalline silicon is deposited on the surface (5) and in that a top layer (13, 14) comprising metal is deposited on this base layer, which top layer consists of a barrier layer (13) of TiW and a layer (14) of aluminium.
Claim 4
Dependent Claim 36 words
A method as claimed in claim 1, characterized in that the electrode (18) is formed in a package of layers (12, 13, 14, 17) of which the upper layer (17) is a layer of insulating material.
Claim 5
Dependent Claim 27 words
A method as claimed in claim 3, characterized in that the electrode is formed in a layer package whose upper layer (17) is made of silicon oxide.
Claim 6
Dependent Claim 110 words
A method as claimed in claim 3, characterized in that an electrode (18) is formed in the package of layers (12, 13, 14, 17), which electrode at the area of the surface region (16) comprises a number of substantially parallel strip-shaped portions (18A, 18B, 18C . . .) which are arranged with mutual interspacings of less than 2 μm, after which a layer of insulating material is deposited over the strip-shaped portions and is subsequently subjected to an anisotropic etching treatment until said layer has been removed from the upper layer of the electrode (18) and insulating edge portions have been formed on the lateral faces of the strip-shaped portions.

References Cited (Backward Citations)

US4889828A Cited
US5006476A Cited
US5128271A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-04-10 1998-10-10 1999-04-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-04-10 2002-10-10 2003-04-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-04-10 2006-10-10 2007-04-11 $7700.00 Window Closed / Lapsed

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