Semiconductor memory device using compensation capacitors

Claim 1

A semiconductor memory device comprises a memory cell array for memorizing bit information at each memory cell as a storage state of charge, to be inputted or outputted thereto in response to changes in potential in corresponding word line and bit line arrays, said bit line array comprising a plurality of bit line pairs, a plurality of sense amplifiers, one of said sense amplifiers being connected to each pair of bit lines in said bit line array for charging or discharging each memory cell of said memory cell array, a sense amplifier driver connected between a power source line and ground line for applying a driving voltage from said power source line to each sense amplifier in response to inputted clock signals, and a plurality of compensation capacitor pairs, at least one of which is formed by making an electrode line crossed over one of said pairs of bit lines through an inter-layer insulation film, and said electrode line is simultaneously formed when said word line arrays are formed and is connected to said ground line of said sense amplifier driver whereby each pair of compensation capacitors varies a potential level between each pair of bit lines in accordance with a change in potential of said ground line so that said change in potential of said ground line is negated in each sense amplifier.