Memory array of integrated circuits capable of replacing faulty cells with a spare

Claim 1

A fault tolerant data storage system comprising: a) a plurality of primary integrated circuits; b) a spare integrated circuit having a data terminal, each of said primary and spare integrated circuits comprising an array of memory locations arranged in rows and in columns, random of said integrated circuits having random columns which are faulty; c) a plurality of data line means connected to respective of said primary integrated circuits for writing data to or reading data from said primary integrated circuits in parallel; d) means for generating logical column addresses one-at-a-time; e) programmable electronic means for converting each logical column address to a set of physical column addresses, one for each primary integrated circuit and one for said spare integrated circuit, at least some of said logical column addresses of each set being skewed relative to each other and relative to the corresponding physical column address such that, for each logical column address, no two faulty columns have the same logical column address and said logical column address of each faulty column corresponds to a same logical column address of said spare integrated circuit; f) first identifying means for identifying which of said primary integrated circuits has a faulty column at the physical column address generated for that primary integrated circuit; and g) electronically controllable means responsive to said first identifying means for connecting the data line means for that integrated circuit to said data terminal of the spare integrated circuit.