Clock signal conditioning circuit

Claim 2

A clock signal conditioning circuit, comprising: an input node for receiving an applied clock signal; an output node for producing thereat a conditioned clock signal; edge detector means for detecting edges in the applied clock signal, wherein the edge detector means comprises a first edge detector for detecting an edge of a first polarity, and a second edge detector for detecting an edge of a second polarity opposite to the first polarity; bistable means for forming at the output node a clock signal in response to the edge detector means; and timer means for inhibiting switching of the bistable means for a predetermined time following detection by the edge detector means of an edge, wherein the timer means comprises a first monostable pulse generator arranged to be triggered in response to the first edge detector and having an output coupled to disable the second edge detector, and a second monostable pulse generator arranged to be triggered in response to the second edge detector and having an output coupled to disable the first edge detector.

Claim 3

A clock signal conditioning circuit according to claim 1 further comprising pulse stretching means coupled to the edge detector means for stretching pulses of the conditioned clock signal.

Claim 4

A clock signal conditioning circuit, comprising: an input node for receiving an applied clock signal; an output node for producing thereat a conditioned clock signal; edge detector means for detecting edges in the applied clock signal, wherein the edge detector means comprises a first edge detector for detecting an edge of a first polarity, and a second edge detector for detecting an edge of a second polarity opposite to the first polarity; bistable means for forming at the output node a clock signal in response to the edge detector means; and timer means for inhibiting switching of the bistable means for a predetermined time following detection by the edge detector means of an edge, wherein the timer means comprises: a first monostable pulse generator arranged to be triggered in response to the first edge detector; a second monostable pulse generator arranged to be triggered in response to the second edge detector; first logic means having inputs coupled to the output of the first edge detector and to the outputs of the first and second monostable pulse generators and having an output coupled to a first input of the bistable means; and second logic means having inputs coupled to the output of the second edge detector and to the outputs of the first and second monostable pulse generators and having an output coupled to a second input of the bistable means.

Claim 5

A clock signal conditioning circuit, comprising: an input node for receiving an applied clock signal; an output node for producing thereat a conditioned clock signal; edge detector means for detecting edges in the applied clock signal, wherein the edge detector means comprises a first edge detector for detecting an edge of a first polarity, and a second edge detector for detecting an edge of a second polarity opposite to the first polarity; bistable means for forming at the output node a clock signal in response to the edge detector means; and timer means for inhibiting switching of the bistable means for a predetermined time following detection by the edge detector means of an edge, wherein the timer means comprises: a first monostable pulse generator arranged to be triggered in response to the first edge detector; a second monostable pulse generator arranged to be triggered in response to the second edge detector; first logic means having inputs coupled to the output of the first edge detector and to the outputs of the first and second monostable pulse generators and having an output coupled to a first input of the bistable means; and second logic means having inputs coupled to the output of the second edge detector and to the outputs of the first and second monostable pulse generators and having an output coupled to a second input of the bistable means.

Claim 6

A clock signal conditioning circuit according to claim 3 arranged to produce a signal having a frequency which is an integer multiple of the applied clock signal frequency and comprising a frequency divider means coupled to receive the signal and to produce therefrom another signal having a desired frequency dependent on the frequency of the applied clock signal.

Claim 7

A clock signal conditioning circuit according to claim 1 wherein the bistable means comprises a data latch.

Claim 8

A clock signal conditioning circuit according to claim 1 wherein the bistable means comprises a flip-flop.

Claim 9

A clock signal conditioning circuit according to claim 1 arranged to produce a signal having a frequency which is an integer multiple of the applied clock signal frequency and comprising a frequency divider means coupled to receive the signal and to produce therefrom another signal having a desired frequency dependent on the frequency of the applied clock signal.