US5428746A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated microprocessor unit generating separate memory and input-output device control signals
Assignee: IXYS Intl Ltd
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Filing: 1992-03-23
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Granted: 1995-06-27
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Expires: 2012-03-23
Abstract
Abstract A microprocessor formed on a single integrated circuit chip has separate sets of terminals providing read and write control timing signals to external memory and input-output devices. The memory control timing signals are generated at a rate as high as the memory devices will allow. The input-output device timing signals are provided at a rate as high as the input-output devices will allow, usually significantly lower rate than that of the memory devices. This then allows the memory transactions to occur at a rate that does not need to be reduced because of slower input-output devices in the same system. The need for external logic is significantly reduced by providing the memory timing signals in a form that is actually input to the memory devices, and by including a capability of providing timing signals to a number of different types of input-output devices having different control signal timing protocol requirements. A computer system using such a microprocessor unit is also described.
Inventors
- 👤 Monte J. Dalrymple
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:27
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217; G06F13/4221; G06F13/423; G06F13/4234; G06F13/4243
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
299 words
As part of a digital processor architecture including a central processing unit (CPU) interconnected with at least one random access memory device and at least one input-output (I/O) device through a common address and data bus structure, a system for providing control of reading from and writing to said at least one memory device and said at least one I/O device, comprising: means within said CPU that is responsive to an instruction to read from or write to said at least one memory device over said bus structure for generating and communicating to said at least one memory device a first set of control signals with a first timing, and means within said CPU that is responsive to an instruction to read from or write to said at least one I/O device over said bus structure for generating and communicating to said at least one I/O device a second set of control signals that are separate from the first set of control signals and have a second timing different from the first timing, said second control signal set generating means including means responsive to a register field for generating read and write timing signals with one of at least two different I/O device signal protocols as specified by contents of said register field, wherein said first and second control signal set generating means are characterized by separately generating said first and second sets of control signals, respectively, whereby the speed of reading and writing operations can be optimized for memory and I/O devices having different data access speeds, and whereby I/O devices having any one of said at least two different signal protocols may be connected directly to said CPU without requiring additional logic outside of said CPU to convert its I/O control signals into that of another protocol.
Claim 2
Dependent Claim
299 words
As part of a digital processor architecture including a central processing unit (CPU) interconnected with at least one random access memory device and at least one input-output (I/O) device through a common address and data bus structure, a system for providing control of reading from and writing to said at least one memory device and said at least one I/O device, comprising: means within said CPU that is responsive to an instruction to read from or write to said at least one memory device over said bus structure for generating and communicating to said at least one memory device a first set of control signals with a first timing, and means within said CPU that is responsive to an instruction to read from or write to said at least one I/O device over said bus structure for generating and communicating to said at least one I/O device a second set of control signals that are separate from the first set of control signals and have a second timing different from the first timing, said second control signal set generating means including means responsive to a register field for generating read and write timing signals with one of at least two different I/O device signal protocols as specified by contents of said register field, wherein said first and second control signal set generating means are characterized by separately generating said first and second sets of control signals, respectively, whereby the speed of reading and writing operations can be optimized for memory and I/O devices having different data access speeds, and whereby I/O devices having any one of said at least two different signal protocols may be connected directly to said CPU without requiring additional logic outside of said CPU to convert its I/O control signals into that of another protocol.
Claim 3
Dependent Claim
32 words
The system of claim 1 wherein said I/O device control signal generating means includes a register containing information specifying one of a plurality of formats of said second set of control signals.
Claim 4
Dependent Claim
53 words
The system of claim 2 wherein said I/O device control signal generating means includes a state machine connected to receive the format information contained in said register, thereby to generate said second set of control signals with a specified one of a plurality formats in accordance with the information contained in said register.
Claim 5
Dependent Claim
59 words
The system of claim 1 which additionally comprises means within said CPU for supplying said at least one memory device with a first clock signal, and means within said CPU for simultaneously supplying said at least one I/O device with a second clock signal having a frequency that is controllable independently of a frequency of said first clock signal.
Claim 6
Dependent Claim
56 words
The system of claim 1 wherein said first control signal set generating means includes means for generating timing reference signals connected directly to said at least one memory device to strobe an address thereinto from said address bus structure, whereby additional logic external of the CPU is made unnecessary to generate said timing and reference signals.
Claim 7
Dependent Claim
30 words
The system of claim 1 wherein each of said CPU, said at least one memory device and said at least one I/O device are formed on separate integrated circuit chips.
Claim 8
Dependent Claim
30 words
The system of claim 5 wherein each of said CPU, said at least one memory device and said at least one I/O device are formed on separate integrated circuit chips.
Claim 9
Dependent Claim
46 words
The system of claim 5 which additionally comprises means within said CPU that is responsive to a receipt of instructions for decoding and executing said instructions, said decoding and executing means being operated with said first timing, said second timing being slower than said first timing.
Claim 10
Dependent Claim
22 words
The system of claim 1 which additionally comprises means receiving data from said at least one memory device for providing said instructions.
Claim 11
Dependent Claim
195 words
A processor formed on a single integrated circuit chip, comprising: means receiving a fixed frequency clock signal for providing an internal clock signal and a variable frequency clock signal, said variable frequency clock signal having a frequency set by a first control signal that is less than that of said internal clock signal, means receiving an instruction for decoding said instruction, said decoding means being operated from said internal clock signal, means receiving decoded instructions from said decoding means for executing said instructions, said executing means being operated from said internal clock signal, means responsive to a second control signal and to an input-output device read or write instruction decoded by said decoding means for generating input-output circuit timing signals according to one of a plurality of protocols designated by said second control signal, said input-output timing signal generating means being operated from said variable frequency clock signal, means responsive to a memory device read or write instruction decoded by said decoding means for generating memory address strobe signals, said memory strobe signal generating means being operated from said internal clock signal, and means including a register for providing said first and second control signals.
Claim 12
Dependent Claim
195 words
A processor formed on a single integrated circuit chip, comprising: means receiving a fixed frequency clock signal for providing an internal clock signal and a variable frequency clock signal, said variable frequency clock signal having a frequency set by a first control signal that is less than that of said internal clock signal, means receiving an instruction for decoding said instruction, said decoding means being operated from said internal clock signal, means receiving decoded instructions from said decoding means for executing said instructions, said executing means being operated from said internal clock signal, means responsive to a second control signal and to an input-output device read or write instruction decoded by said decoding means for generating input-output circuit timing signals according to one of a plurality of protocols designated by said second control signal, said input-output timing signal generating means being operated from said variable frequency clock signal, means responsive to a memory device read or write instruction decoded by said decoding means for generating memory address strobe signals, said memory strobe signal generating means being operated from said internal clock signal, and means including a register for providing said first and second control signals.
Claim 13
Dependent Claim
34 words
The processor according to claim 10 wherein said input-output timing signal generating means includes a first state machine having the second control signal and the decoded input-output device read or write instruction as inputs.
Claim 14
Dependent Claim
29 words
The processor according to claim 11 wherein said input-output timing signal generating means includes a second state machine having the decoded memory device read or write instruction as inputs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-26 | 1998-12-26 | 1999-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-26 | 2002-12-26 | 2003-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-26 | 2006-12-26 | 2007-06-27 | $7700.00 | Window Closed / Lapsed |