Patent US5428790A successfully refreshed from Google Patents.
US5428790A
Expired / Lapsed
US
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Computer power management system
Assignee: Fujitsu Personal Systems Inc
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Filing: 1993-10-08
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Granted: 1995-06-27
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Expires: 2013-10-08
Abstract
Abstract A low power management system including both hardware and software for a battery powered portable computer. The low power management system powers down various sections of the computer when they are not used. The low power management system is controlled by a control program in the microprocessor of the computer. The low power management system includes the capability to turn off clock signals to various sections of the computer based upon demand. Also included is the capability to turn on clock signals based upon demand. The low power management system also includes the capability to turn on the computer upon a press of a key on the computer keyboard. The low power management system monitors software application programs for keyboard activity so as to turn off the microprocessor in the computer in response to a loop looking for a keypress and certain other loops which can be monitored without use of the microprocessor.
Inventors
- 👤 Leroy D. Harper
- 👤 Grayson C. Schlichting
- 👤 Douglas A. Hooks
- 👤 Ian H. S. Culimore
- 👤 Gavin A. Bradshaw
- 👤 Biswa R. Banerjee
- 👤 John P. Fairbanks
- 👤 Roderick W. Stone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:28
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/324; G06F1/04; G06F1/08; G06F1/325; G06F1/3265; G06F1/3287; Y; Y02; Y02D; Y02D10/00; Y02D30/00; Y02D30/50
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
109 words
A method for operating a processor for operating at a plurality of clock frequencies, comprising: providing clock signals to the processor, the clock signals being at a frequency determined by a variable supply voltage level; providing a first supply voltage level, thereby operating the processor at a corresponding first clock frequency; determining a duration of elapsed time that the processor has been operating at the first clock frequency; and upon determining that the duration of elapsed time exceeds a predetermined amount, providing a second supply voltage level higher than the first supply voltage level, thereby operating the processor at a second clock frequency higher than the first clock frequency.
Claim 2
Independent Claim
109 words
A method for operating a processor for operating at a plurality of clock frequencies, comprising: providing clock signals to the processor, the clock signals being at a frequency determined by a variable supply voltage level; providing a first supply voltage level, thereby operating the processor at a corresponding first clock frequency; determining a duration of elapsed time that the processor has been operating at the first clock frequency; and upon determining that the duration of elapsed time exceeds a predetermined amount, providing a second supply voltage level higher than the first supply voltage level, thereby operating the processor at a second clock frequency higher than the first clock frequency.
Claim 3
Dependent Claim
33 words
The method of claim 1, wherein the first supply voltage level is in the range of about 2 to 3 volts, and the second supply voltage level is at least about 5 volts.
Claim 4
Dependent Claim
21 words
The method of claim 1, wherein the second clock frequency is more than three times greater than the first clock frequency.
Claim 5
Dependent Claim
26 words
The method of claim 1, further comprising the step of providing a third supply voltage level equal to about zero, thereby stopping operation of the processor.
Claim 6
Dependent Claim
65 words
The method of claim 4, wherein the processor is a part of a computer including a manual input device, and wherein the step of providing a third supply voltage level comprises: determining a duration of time that no computer activity or manual input device activity has taken place; and when the determined duration of time exceeds a predetermined amount, providing the third supply voltage level.
Claim 7
Dependent Claim
40 words
The method of claim 1, further comprising, prior to the first step of providing: stopping the processor by supplying a clock signal of about zero frequency to the processor, while maintaining power to a display device connected to the processor.
Claim 8
Dependent Claim
156 words
A power system for a computer system having a processor, the processor operating at at least two clock frequencies, each clock frequency being associated with a particular supply voltage level for clocking the processor, comprising: a supply voltage circuit for generating at least two different supply voltage levels for clocking the processor, a first supply voltage level being less than the second supply voltage level; means for determining a duration of elapsed time the processor has been operating at a first clock frequency associated with the first supply voltage level; and means for controlling the supply voltage circuit to supply the second supply voltage level for clocking the processor in place of the first supply voltage level when the duration of elapsed time exceeds a predetermined amount, the processor thereby operating at a second clock frequency associated with the second supply voltage level, and wherein the second clock frequency is higher than the first clock frequency.
Claim 9
Dependent Claim
156 words
A power system for a computer system having a processor, the processor operating at at least two clock frequencies, each clock frequency being associated with a particular supply voltage level for clocking the processor, comprising: a supply voltage circuit for generating at least two different supply voltage levels for clocking the processor, a first supply voltage level being less than the second supply voltage level; means for determining a duration of elapsed time the processor has been operating at a first clock frequency associated with the first supply voltage level; and means for controlling the supply voltage circuit to supply the second supply voltage level for clocking the processor in place of the first supply voltage level when the duration of elapsed time exceeds a predetermined amount, the processor thereby operating at a second clock frequency associated with the second supply voltage level, and wherein the second clock frequency is higher than the first clock frequency.
Claim 10
Dependent Claim
74 words
The system of claim 7, further comprising a timing signal generator operatively connected to the supply voltage circuit for receiving the at least two different supply voltage levels, and having an output terminal connected to the processor for providing at least two clock signals to the processor, a first clock signal being at the first clock frequency of the processor and a second clock signal being at the second clock frequency of the processor.
Claim 11
Dependent Claim
15 words
The system of claim 8 wherein the timing signal generator includes a voltage controlled oscillator.
Claim 12
Dependent Claim
47 words
The system of claim 7, wherein the computer system further includes a display device connected to the processor, the power system further comprising means for stopping the processor by supplying a clock signal of about zero frequency to the processor while maintaining power to the display device.
Claim 13
Independent Claim
174 words
A method for reducing power consumed by a computer having a processor for executing at least one user application program and having a manual input device for inputting data to the processor, the application program generating processor interrupts for receiving data at the processor from the manual input device, comprising the steps of: executing the application program at a first operating frequency of the processor; during the execution of the application program, counting a first number of the processor interrupts generated by the application program during a first time interval of predetermined duration; then counting a second number of the processor interrupts generated by the application program during a second time interval of equal duration and subsequent to the first; if the first number is within a predetermined value of the second number, then determining if the processor is executing a predetermined activity; and if the processor is executing the predetermined activity, then operating the processor to continue executing the application program but at a second operating frequency lower than the first operating frequency.
Claim 14
Independent Claim
174 words
A method for reducing power consumed by a computer having a processor for executing at least one user application program and having a manual input device for inputting data to the processor, the application program generating processor interrupts for receiving data at the processor from the manual input device, comprising the steps of: executing the application program at a first operating frequency of the processor; during the execution of the application program, counting a first number of the processor interrupts generated by the application program during a first time interval of predetermined duration; then counting a second number of the processor interrupts generated by the application program during a second time interval of equal duration and subsequent to the first; if the first number is within a predetermined value of the second number, then determining if the processor is executing a predetermined activity; and if the processor is executing the predetermined activity, then operating the processor to continue executing the application program but at a second operating frequency lower than the first operating frequency.
Claim 15
Dependent Claim
68 words
The method of claim 11, further comprising: supplying voltage dependent clock signals to the processor, thereby determining the operating frequency of the processor; providing a first voltage level, thereby causing supply of clock signals of the first operating frequency to the processor; and providing a second voltage level lower than the first voltage level, thereby causing supply of clock signals of the second operating frequency to the processor.
Claim 16
Independent Claim
130 words
A method of operating a computer having a display device, a manual input device, and a processor, the processor operating at at least two clock signal frequencies, comprising the steps of: stopping the processor by stopping supply of a clock signal to the processor, while maintaining power to the display device and to the manual input device; then, resuming operation of the processor by supplying a lower of the two clock signal frequencies to the processor; determining a duration of elapsed time that the processor has been operating at the lower of the two clock signal frequencies; and then, supplying the higher of the two clock signal frequencies to the processor in place of the lower of the two clock signal frequencies if the elapsed time exceeds a predetermined value.
Claim 17
Independent Claim
130 words
A method of operating a computer having a display device, a manual input device, and a processor, the processor operating at at least two clock signal frequencies, comprising the steps of: stopping the processor by stopping supply of a clock signal to the processor, while maintaining power to the display device and to the manual input device; then, resuming operation of the processor by supplying a lower of the two clock signal frequencies to the processor; determining a duration of elapsed time that the processor has been operating at the lower of the two clock signal frequencies; and then, supplying the higher of the two clock signal frequencies to the processor in place of the lower of the two clock signal frequencies if the elapsed time exceeds a predetermined value.
Claim 18
Dependent Claim
137 words
A power supply system for a computer system having a display device and a manual input device connected to a processor, the processor operating at at least two clock signal frequencies, comprising: means for stopping supply of a clock signal to the processor while maintaining power to the display device and manual input device, thereby stopping the processor; means for supplying a lower of the two clock signal frequencies to the processor, thereby resuming operation of the processor; means for determining a duration of elapsed time that the processor has been operating at the lower of the two clock signal frequencies; and means for supplying the higher of the two clock signal frequencies to the processor in place of the lower of the two clock signal frequencies if the duration of elapsed time exceeds a predetermined value.
Claim 19
Dependent Claim
137 words
A power supply system for a computer system having a display device and a manual input device connected to a processor, the processor operating at at least two clock signal frequencies, comprising: means for stopping supply of a clock signal to the processor while maintaining power to the display device and manual input device, thereby stopping the processor; means for supplying a lower of the two clock signal frequencies to the processor, thereby resuming operation of the processor; means for determining a duration of elapsed time that the processor has been operating at the lower of the two clock signal frequencies; and means for supplying the higher of the two clock signal frequencies to the processor in place of the lower of the two clock signal frequencies if the duration of elapsed time exceeds a predetermined value.
References Cited (Backward Citations)
US3909685A
Cited
US3941989A
Cited
US4137563A
Cited
US4129091A
Cited
US4203153A
Cited
US4279020A
Cited
US4455623A
Cited
US4758945A
Cited
US4748559A
Cited
US4435761A
Cited
US4409665A
Cited
US4317181A
Cited
US4463440A
Cited
US4479191A
Cited
GB2080585A
Cited
US4615005A
Cited
US4554630A
Cited
US4570219A
Cited
US4545030A
Cited
US4870570A
Cited
US4841440A
Cited
US4809163A
Cited
US4612418A
Cited
US4747041A
Cited
US4698748A
Cited
US4669059A
Cited
US4573117A
Cited
US4780843A
Cited
US4819164A
Cited
US4644300A
Cited
US4825407A
Cited
US4825358A
Cited
US4851987A
Cited
EP0229692A2
Cited
US4907150A
Cited
US4823292A
Cited
EP0265209A1
Cited
US5025387A
Cited
US5121500A
Cited
US5041964A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-26 | 1998-12-26 | 1999-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-26 | 2002-12-26 | 2003-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-26 | 2006-12-26 | 2007-06-27 | $7700.00 | Window Closed / Lapsed |