Computer system module

Claim 2

A Computer System core module comprising: a single printed circuit board; at least one processor mounted on the printed circuit board; a read-write buffer mounted on the printed circuit board and connected to the at least one processor; memory devices mounted on the printed circuit board and connected to the read-write buffer; clock means for generating clock signals and for conveying the clock signals to the at least one processor, the clock means mounted on the printed circuit board; receiving means for receiving an asynchronous reset signal onto the printed circuit board, the receiving means mounted on the printed circuit board, said asynchronous reset signal being generated external to the printed circuit board; reset logic system means mounted on the printed circuit board for generating synchronous reset signals and for conveying the synchronous reset signals to the at least one processor and to the read-write buffer in response to the asynchronous reset signal; and a connector on the printed circuit board for plugging the printed circuit board into a receptacle on a motherboard of an external system, for conveying signals from the printed circuit board to the motherboard, and for conveying signals from the motherboard to the printed circuit board, including conveying an externally-provided asynchronous reset signal from the motherboard to the reset logic system on the printed circuit board.

Claim 3

A computer system core module according to claim 1, wherein: one of the at least one processors is a co-processor.

Claim 4

A computer system core module according to claim 1, wherein: the external system is a workstation.

Claim 5

A computer system core module according to claim 1, wherein: at least one of the at least one processors generates interrupt request signals for the reset logic system; the read-write buffer generates acknowledge signals for the reset logic system; the reset logic system synchronizes the interrupt request signals and the acknowledge signals in response to a configuration signal received on the printed circuit board from the external system.

Claim 6

A computer system core module according to claim 4, wherein: the reset logic system buffers and resynchronizes the interrupt request signals and the acknowledge signals to control timing margins between the interrupt request signals and the acknowledge signals.

Claim 7

A computer system core module according to claim 1, wherein: the reset logic system generates a configuration enable signal configuring states of the various elements on the printed circuit board in conjunction with generating the reset signals for the at least one processor and the read-write buffer.

Claim 8

A computer system core module according to claim 1, wherein: the reset logic system generates a signal for setting the at least one processor in a tristate mode, thereby allowing an off-board probe to drive the read-write buffer.

Claim 9

A computer system core module according to claim 1, wherein: the read-write buffer is disposed at a location on the printed circuit board wherein said read-write buffer has the shortest possible connection path to the connector and to the at least one processor.

Claim 10

A computer system core module comprising: a single printed circuit board; at least one processor mounted on the printed circuit board; a read-write buffer mounted on the printed circuit board and connected to the at least one processor; memory devices mounted on the printed circuit board and connected to the read-write buffer; clock means or generating clock signals and for conveying the clock signals to the at least one processor, the clock means mounted on the printed circuit board; receiving means for receiving an asynchronous reset signal onto the printed circuit board, the receiving means mounted on the printed circuit board, said asynchronous reset signal being generated external to the printed circuit board; reset logic system means mounted on the printed circuit board for generating synchronous reset signals and for conveying the synchronous reset signals to the at least one processor and to the read-write buffer in response to the asynchronous reset signal; and a connector on the printed circuit board for plugging the printed circuit board into a receptacle on a motherboard of an external system, for conveying signals from the printed circuit board to the motherboard, and for conveying signals from the motherboard to the printed circuit board, including conveying an externally-provided asynchronous reset signal from the motherboard to the reset logic system on the printed circuit board, wherein: the signal composition of the module includes: a configuration buffer enable signal (CfgEn); a page write signal (PgWrt); a block match signal (BlkMtch); a write mask signal (WrMsk); and a test enable signal (TestEn).

Claim 11

A computer system core module comprising: a single printed circuit board; at least one processor mounted on the printed circuit board; a read-write buffer mounted on the printed circuit board and connected to the at least one processor; memory devices mounted on the printed circuit board and connected to the read-write buffer; clock means or generating clock signals and for conveying the clock signals to the at least one processor, the clock means mounted on the printed circuit board; receiving means for receiving an asynchronous reset signal onto the printed circuit board, the receiving means mounted on the printed circuit board, said asynchronous reset signal being generated external to the printed circuit board; reset logic system means mounted on the printed circuit board for generating synchronous reset signals and for conveying the synchronous reset signals to the at least one processor and to the read-write buffer in response to the asynchronous reset signal; and a connector on the printed circuit board for plugging the printed circuit board into a receptacle on a motherboard of an external system, for conveying signals from the printed circuit board to the motherboard, and for conveying signals from the motherboard to the printed circuit board, including conveying an externally-provided asynchronous reset signal from the motherboard to the reset logic system on the printed circuit board, wherein: the signal composition of the module includes: a configuration buffer enable signal (CfgEn); a page write signal (PgWrt); a block match signal (BlkMtch); a write mask signal (WrMsk); and a test enable signal (TestEn).

Claim 12

A Computer System core module comprising: a single printed circuit board; two processors on the printed circuit board; a read-write buffer on the printed circuit board and connected to the two processors; memory devices on the printed circuit board and connected to the read-write buffer; clock means on the printed circuit board for generating clock signals and for conveying the clock signals to the two processors; means for receiving, from off the printed circuit board, an asynchronous reset signal; a connector on the printed circuit board for plugging the printed circuit board into a receptacle on a motherboard of an external system, for conveying signals from the printed circuit board to the motherboard, and for conveying signals from the motherboard to the printed circuit board, including conveying an externally-provided asynchronous reset signal from the motherboard to the reset logic system on the printed circuit board; and reset logic system means mounted on the printed circuit board for generating synchronous reset signals for synchronously resetting the two processors and the read-write buffer in response to the asynchronous reset signal; wherein: at least one of the two processors generates interrupt request signals to the reset logic system; the read-write buffer generates acknowledge signals to the reset logic system; the reset logic system synchronizes the interrupt request signals and the acknowledge signals; the reset logic system buffers and resynchronizes the interrupt request signals and the acknowledge signals to control timing margins between the interrupt request signals and the acknowledge signals; the reset logic system generates a configuration enable signal configuring states of the various elements on the printed circuit board in conjunction with generating the synchronous reset signals; and the reset logic system generates a signal to set the two processors in a tristate mode in response to signals generated by a system located off of the printed circuit board, thereby allowing a probe external to the printed circuit board to drive the read-write buffer.

Claim 13

A Computer System core module comprising: a single printed circuit board; two processors on the printed circuit board; a read-write buffer on the printed circuit board and connected to the two processors; memory devices on the printed circuit board and connected to the read-write buffer; clock means on the printed circuit board for generating clock signals and for conveying the clock signals to the two processors; means for receiving, from off the printed circuit board, an asynchronous reset signal; a connector on the printed circuit board for plugging the printed circuit board into a receptacle on a motherboard of an external system, for conveying signals from the printed circuit board to the motherboard, and for conveying signals from the motherboard to the printed circuit board, including conveying an externally-provided asynchronous reset signal from the motherboard to the reset logic system on the printed circuit board; and reset logic system means mounted on the printed circuit board for generating synchronous reset signals for synchronously resetting the two processors and the read-write buffer in response to the asynchronous reset signal; wherein: at least one of the two processors generates interrupt request signals to the reset logic system; the read-write buffer generates acknowledge signals to the reset logic system; the reset logic system synchronizes the interrupt request signals and the acknowledge signals; the reset logic system buffers and resynchronizes the interrupt request signals and the acknowledge signals to control timing margins between the interrupt request signals and the acknowledge signals; the reset logic system generates a configuration enable signal configuring states of the various elements on the printed circuit board in conjunction with generating the synchronous reset signals; and the reset logic system generates a signal to set the two processors in a tristate mode in response to signals generated by a system located off of the printed circuit board, thereby allowing a probe external to the printed circuit board to drive the read-write buffer.

Claim 14

A computer system core module according to claim 10, wherein: one of the at least one processors is a co-processor.

Claim 15

A computer system core module according to claim 10, wherein: the external system is a workstation.

Claim 16

A computer system core module according to claim 10, wherein: the physical location of the read-write buffer is chosen to provide the shortest possible connection path to the connector and to the at least one processor.

Claim 17

A computer system core module comprising: a single printed circuit board; two processors on the printed circuit board; a read-write buffer on the printed circuit board and connected to the two processors; memory devices on the printed circuit board and connected to the read-write buffer; clock means on the printed circuit board for generating clock signals and for conveying the clock signals to the two processors; means for receiving, from off the printed circuit board, an asynchronous reset signal; a connector on the printed circuit board for plugging the printed circuit board into a receptacle on a motherboard of an external system, for conveying signals from the printed circuit board to the motherboard, and for conveying signals from the motherboard to the printed circuit board, including conveying an externally-provided asynchronous reset signal from the motherboard to the reset logic system on the printed circuit board; and reset logic system means on the printed circuit board for generating synchronous reset signals for synchronously resetting the two processors and the read-write buffer in response to the asynchronous reset signal; wherein: at least one of the two processors generates interrupt request signals to the reset logic system; the read-write buffer generates acknowledge signals to the reset logic system; the reset logic system synchronizes the interrupt request signals and the acknowledge signals; the reset logic system buffers and resynchronizes the interrupt request signals and the acknowledge signals to control timing margins between the interrupt request signals and the acknowledge signals; the reset logic system generates a configuration enable signal configuring states of the various elements on the printed circuit board in conjunction with generating the synchronous reset signals; and the reset logic system generates a signal to set the two processors in a tristate mode in response to signals generated by an off-board system, thereby allowing a probe external to the printed circuit board to drive the read-write buffer, wherein: the signal composition of the module includes: a configuration buffer enable signal (CfgEn); a page write signal (PgWrt); a block match signal (BlkMtch); a write mask signal (WrMsk); and a test enable signal (TestEn).

Claim 18

A computer system core module comprising: a single printed circuit board; two processors on the printed circuit board; a read-write buffer on the printed circuit board and connected to the two processors; memory devices on the printed circuit board and connected to the read-write buffer; clock means on the printed circuit board for generating clock signals and for conveying the clock signals to the two processors; means for receiving, from off the printed circuit board, an asynchronous reset signal; a connector on the printed circuit board for plugging the printed circuit board into a receptacle on a motherboard of an external system, for conveying signals from the printed circuit board to the motherboard, and for conveying signals from the motherboard to the printed circuit board, including conveying an externally-provided asynchronous reset signal from the motherboard to the reset logic system on the printed circuit board; and reset logic system means on the printed circuit board for generating synchronous reset signals for synchronously resetting the two processors and the read-write buffer in response to the asynchronous reset signal; wherein: at least one of the two processors generates interrupt request signals to the reset logic system; the read-write buffer generates acknowledge signals to the reset logic system; the reset logic system synchronizes the interrupt request signals and the acknowledge signals; the reset logic system buffers and resynchronizes the interrupt request signals and the acknowledge signals to control timing margins between the interrupt request signals and the acknowledge signals; the reset logic system generates a configuration enable signal configuring states of the various elements on the printed circuit board in conjunction with generating the synchronous reset signals; and the reset logic system generates a signal to set the two processors in a tristate mode in response to signals generated by an off-board system, thereby allowing a probe external to the printed circuit board to drive the read-write buffer, wherein: the signal composition of the module includes: a configuration buffer enable signal (CfgEn); a page write signal (PgWrt); a block match signal (BlkMtch); a write mask signal (WrMsk); and a test enable signal (TestEn).

Claim 19

A computer system module to be plugged into a motherboard, the computer system module comprising: a single printed circuit board; a control bus mounted on the single printed circuit board; a data bus mounted on the single printed circuit board; an address bus mounted on the single printed circuit board; a central processing unit mounted on the single printed circuit board, capable of reduced instruction set computing, and having a cache interface and a cache control system, wherein the central processing unit is in electrical communication with the control bus, the data bus, and the address bus; a floating-point accelerator mounted on the single printed circuit board and in electrical communication with the control bus and the data bus to permit high-speed floating point capability of the central processing unit; a read-write buffer mounted on the single printed circuit board and electrically coupled to the control bus, the data bus, and the address bus for buffering read and write operations which utilize the data bus and the address bus; a data cache mounted on the single printed circuit board and in electrical communication with the cache interface of the central processing unit through the control bus, the data bus, and the address bus such that electrical data cache signals are transmitted between the central processing unit and the data cache under the control, at least in part, of the cache control system of the central processing unit; an instruction cache mounted on the single printed circuit board and in electrical communication with the cache interface of the central processing unit through the control bus, the data bus, and the address bus such that electrical instruction cache signals are transmitted between the central processing unit and the instruction cache under the control, at least in part, of the cache control system of the central processing unit; a clock generator mounted on the single printed circuit board and in electrical communication with the central processing unit for generating clock signals for the central processing unit, the floating point accelerator, and the read-write buffer in response to an external signal received from the motherboard; memory buffers mounted on the single printed circuit board for buffering a plurality of electrical signals transferred between the motherboard and at least one of the central processing unit, the floating point accelerator, and the read-write buffer through the control bus by buffering the plurality of electrical signals transferred between the motherboard and the control bus; a reset logic system mounted on the single printed circuit board for generating a synchronous internal reset signal for the central processing unit, the floating point accelerator, and the read-write buffer in response to the an external asynchronous reset signal received by the computer system module from the motherboard; and a connector mounted on the single printed circuit board for permitting electrical connections between the computer system module and the motherboard and for plugging the computer system module into the motherboard thereby electrically coupling the motherboard to the control bus, the data bus, the address bus, the central processing unit, the floating point accelerator, the read-write buffer, the data cache, the instruction cache, the clock generator, the memory buffers, and the reset logic system.

Claim 20

A computer system module to be plugged into a motherboard, the computer system module comprising: a single printed circuit board; a control bus mounted on the single printed circuit board; a data bus mounted on the single printed circuit board; an address bus mounted on the single printed circuit board; a central processing unit mounted on the single printed circuit board, capable of reduced instruction set computing, and having a cache interface and a cache control system, wherein the central processing unit is in electrical communication with the control bus, the data bus, and the address bus; a floating-point accelerator mounted on the single printed circuit board and in electrical communication with the control bus and the data bus to permit high-speed floating point capability of the central processing unit; a read-write buffer mounted on the single printed circuit board and electrically coupled to the control bus, the data bus, and the address bus for buffering read and write operations which utilize the data bus and the address bus; a data cache mounted on the single printed circuit board and in electrical communication with the cache interface of the central processing unit through the control bus, the data bus, and the address bus such that electrical data cache signals are transmitted between the central processing unit and the data cache under the control, at least in part, of the cache control system of the central processing unit; an instruction cache mounted on the single printed circuit board and in electrical communication with the cache interface of the central processing unit through the control bus, the data bus, and the address bus such that electrical instruction cache signals are transmitted between the central processing unit and the instruction cache under the control, at least in part, of the cache control system of the central processing unit; a clock generator mounted on the single printed circuit board and in electrical communication with the central processing unit for generating clock signals for the central processing unit, the floating point accelerator, and the read-write buffer in response to an external signal received from the motherboard; memory buffers mounted on the single printed circuit board for buffering a plurality of electrical signals transferred between the motherboard and at least one of the central processing unit, the floating point accelerator, and the read-write buffer through the control bus by buffering the plurality of electrical signals transferred between the motherboard and the control bus; a reset logic system mounted on the single printed circuit board for generating a synchronous internal reset signal for the central processing unit, the floating point accelerator, and the read-write buffer in response to the an external asynchronous reset signal received by the computer system module from the motherboard; and a connector mounted on the single printed circuit board for permitting electrical connections between the computer system module and the motherboard and for plugging the computer system module into the motherboard thereby electrically coupling the motherboard to the control bus, the data bus, the address bus, the central processing unit, the floating point accelerator, the read-write buffer, the data cache, the instruction cache, the clock generator, the memory buffers, and the reset logic system.

Claim 21

A computer system module as recited in claim 15 wherein the reset logic system sequences central processing unit interrupt requests and read-write acknowledge signals through configuration cycles in response to configuration signals received by the computer system module from the motherboard during a reset.

Claim 22

A computer system module as recited in claim 15 wherein the reset logic system configures the computer system module for testing by setting the central processing unit and the floating point accelerator into a tristate mode thereby to permit an external probe, not part of the computer system module, to drive the data cache, the instruction cache, and the read-write buffer in lieu of the central processing unit.