Semiconductor memory device and manufacturing method of the same

Claim 2

A semiconductor memory device capable of electrically writing and erasing information, comprising: a semiconductor substrate of a first conductivity type having a main surface; a pair of impurity regions of a second conductivity type formed on said main service of said semiconductor substrate and are spaced from each other by a predetermined distance with a channel region therebetween; a first insulating film having a first thickness and formed at least on said channel region; a second insulating film formed at least on a predetermined region of one of said impurity regions and having a second thickness larger than said first thickness; a charge accumulating electrode formed on said first insulating film and said second insulating film, and having first and second ends, and wherein the second insulating film is formed between one of the first and second ends and the one of the impurity regions; and a control electrode formed on said charge accumulating electrode with a third insulating film therebetween.

Claim 3

A semiconductor memory device according to claim 1, wherein said second insulating film has a tapered shape of which thickness gradually reduces toward said channel region.

Claim 4

A semiconductor memory device according to claim 1, wherein said second insulating film is formed of a first film for preventing entry by an external oxidizer and a second film for improving an adherency between said first film and at least one of said charge accumulating electrode and said semiconductor substrate.

Claim 5

A semiconductor memory device second according to claim 1, wherein said second thickness of said second insulating film is determined to prevent passage of electron between said charge accumulating electrode and a pair of said impurity regions in data erasing and writing operations.

Claim 6

A semiconductor memory device according to claim 1, wherein the length of said second insulating film along the main surface of said semiconductor substrate is longer than the length of an oxide film including a gate bird's beak shape and formed between the upper surface of said second insulating film and a lower surface end portion of said charge storage electrode along the main surface of said semiconductor substrate.

Claim 7

A semiconductor memory device according to claim 1, wherein said charge accumulating electrode has a concave upper surface, and said control electrode has a convex lower surface.

Claim 8

A semiconductor memory device according to claim 1, wherein said first thickness of said first insulating film is about 120 Å, and said second thickness of said second insulating film is about 1000 Å.

Claim 9

A semiconductor memory device according to claim 1, wherein oxide films including a gate bird's beak shape are formed between an upper surface of said second insulating film and opposite ends of a lower surface of said charge accumulating electrode.

Claim 10

A semiconductor memory device according to claim 1, wherein said second insulating film is formed on said pair of impurity regions and surrounds said first insulating film.

Claim 11

A semiconductor memory device according to claim 2, wherein said second insulating film is formed of a first film for preventing entry by an external oxidizer and a second film for improving adherence between said first film and at least one of said charge accumulating electrode and said semiconductor substrate.

Claim 12

A semiconductor memory device according to claim 1, wherein said second insulating film includes at least one film selected from the group consisting of a nitride film, a CVD oxide film and a thermal oxide film.

Claim 13

A semiconductor memory device according to claim 1, wherein an interlayer thermal oxide film is formed to cover said control electrode, said charge accumulating electrode and said semiconductor substrate.

Claim 14

A semiconductor memory device according to claim 12, wherein a flattened interlayer insulating film is formed to cover said interlayer thermal oxide film.

Claim 15

A semiconductor memory device capable of electrically writing and erasing information, comprising: a semiconductor substrate of a first conductivity type having a main surface; a pair of impurity regions of a second conductivity type formed on said main surface of said semiconductor substrate and spaced from each other by a predetermined distance with a channel region therebetween; a first insulating film formed at least on said channel region; an oxidizer entry preventing film for intercepting passage of electrons between said charge storage electrode and said pair of impurity regions at the time of writing and erasing information and for preventing entrance by an external oxidizer formed at least on a predetermined region of one of said impurity regions; a charge accumulating electrode formed on said first insulating film and said oxidizer entry preventing film, and having first and second ends, and wherein the second insulating film is formed between one of the first and second ends and the one of the impurity regions; and a control electrode formed on said charge accumulating electrode with a second insulating film therebetween.

Claim 16

A semiconductor memory device capable of electrically writing and erasing information, comprising: a semiconductor substrate of a first conductivity type having a main surface; a pair of impurity regions of a second conductivity type formed on said main surface of said semiconductor substrate and spaced from each other by a predetermined distance with a channel region therebetween; a first insulating film formed at least on said channel region; an oxidizer entry preventing film for intercepting passage of electrons between said charge storage electrode and said pair of impurity regions at the time of writing and erasing information and for preventing entrance by an external oxidizer formed at least on a predetermined region of one of said impurity regions; a charge accumulating electrode formed on said first insulating film and said oxidizer entry preventing film, and having first and second ends, and wherein the second insulating film is formed between one of the first and second ends and the one of the impurity regions; and a control electrode formed on said charge accumulating electrode with a second insulating film therebetween.

Claim 17

A semiconductor memory device according to claim 14, wherein said oxidizer entry preventing film has a tapered shape of which a thickness of the tapered shape gradually reduces toward said channel region.

Claim 18

A semiconductor memory device according to claim 14, wherein said oxidizer entry preventing film has a thickness larger than that of said first insulating film.

Claim 19

A semiconductor memory device according to claim 14, wherein said oxidizer entry preventing film is formed to surround said first insulating film.

Claim 20

A semiconductor memory device according to claim 14, wherein oxide films including a gate bird's beak shape are formed between an upper surface of said oxidizer entry preventing film and opposite ends of a lower surface of said charge accumulating electrode.

Claim 21

A semiconductor memory device according to claim 14, wherein the length of said oxidizer entry preventing film along the main surface of said semiconductor substrate is longer than the length of an oxide film including a gate's bird beak shape and formed between the upper surface of said oxidizer entry preventing film and a lower surface end portion of said charge storage electrode along the main surface of said semiconductor substrate.

Claim 22

A Semiconductor memory device according to claim 14, wherein said charge accumulating electrode has a concave upper surface, and said control electrode has a convex lower surface.

Claim 23

A semiconductor memory device according to claim 14, wherein said oxidizer entry preventing film includes at least one film selected from the group consisting of a nitride film and a thermal oxide film.

Claim 24

A semiconductor memory device according to claim 14, wherein said oxidizer entry preventing film is formed on said first insulating film.

Claim 25

A semiconductor memory device according to claim 14, wherein an interlayer thermal oxide film is formed to cover said control electrode, said charge accumulating electrode and said semiconductor substrate.

Claim 26

A semiconductor memory device according to claim 23, wherein a flattened interlayer insulating film is formed to cover said interlayer thermal oxide film.

Claim 27

A semiconductor memory device capable of electrically writing and erasing information, comprising: a semiconductor substrate of a first conductivity type having a main surface; a pair of impurity regions of a second conductivity type formed on said main surface of said semiconductor substrate and spaced from each other by a prescribed distance with a channel region therebetween; a first insulating film formed at least on said channel region; a second insulating film formed on a prescribed region of at least one of said impurity regions; a charge storage electrode formed on said first insulating film and said second insulating film, and having first and second ends, and wherein the second insulating film is formed between one of the first and second ends and the at least one of said impurity regions; and a control electrode formed on said charge storage electrode with a third insulating film both therebetween.

Claim 28

A semiconductor memory device capable of electrically writing and erasing information, comprising: a semiconductor substrate of a first conductivity type having a main surface; a pair of impurity regions of a second conductivity type formed on said main surface of said semiconductor substrate and spaced from each other by a prescribed distance with a channel region therebetween; a first insulating film formed at least on said channel region; a second insulating film formed on a prescribed region of at least one of said impurity regions; a charge storage electrode formed on said first insulating film and said second insulating film, and having first and second ends, and wherein the second insulating film is formed between one of the first and second ends and the at least one of said impurity regions; and a control electrode formed on said charge storage electrode with a third insulating film both therebetween.

Claim 29

A semiconductor memory device according to claim 1, wherein the first and second thicknesses of the first and second insulating films form a junction, and wherein the junction is located over the one of said pair of impurity regions.

Claim 30

A semiconductor memory device according to claim 1, wherein the first and second thicknesses of said first and second insulating films form a first junction, wherein the one of said pair of impurity regions forms a second junction with said channel region, and wherein the first junction is located substantially over the second junction.

Claim 31

A semiconductor memory device according to claim 1, wherein said charge accumulating electrode includes first and second ends, wherein the first and second thicknesses of the first and second insulating films form a junction, and wherein the junction is located substantially over one of the first and second ends.

Claim 32

A semiconductor memory device, comprising: a substrate having a channel region; first and second impurity regions formed in said substrate on opposite sides of the channel region; a first insulating film having first and second ends, a first thickness and formed at least on the channel region; a second insulating film formed at least on a first predetermined region of said first impurity region and not on the channel region, and having a second thickness larger than the first thickness; a third insulating film formed at least on a second predetermined region of said second impurity region and not on the channel region, and having a third thickness larger than the first thickness; a charge accumulating electrode formed on said first, second and third insulating films; and a control electrode formed on said charge accumulating electrode.

Claim 33

A semiconductor memory device, comprising: a substrate having a channel region; first and second impurity regions formed in said substrate on opposite sides of the channel region; a first insulating film having first and second ends, a first thickness and formed at least on the channel region; a second insulating film formed at least on a first predetermined region of said first impurity region and not on the channel region, and having a second thickness larger than the first thickness; a third insulating film formed at least on a second predetermined region of said second impurity region and not on the channel region, and having a third thickness larger than the first thickness; a charge accumulating electrode formed on said first, second and third insulating films; and a control electrode formed on said charge accumulating electrode.

Claim 34

A semiconductor memory device according to claim 28, wherein the first thickness and the second thickness form a first junction, and the first thickness and the third thickness form a second junction, and wherein the first junction is located over said first impurity region, and the second junction is located over said second impurity region.

Claim 35

A semiconductor memory device according to claim 28, wherein the first thickness and the second thickness form a first junction, and the first thickness and the third thickness form a second junction, and wherein said first impurity region forms a third junction with said channel region, and said second impurity region forms a fourth junction with said channel region, and wherein the first junction is located substantially over the third junction, and the second junction is located substantially over the fourth junction.

Claim 36

A semiconductor memory device according to claim 1, wherein said charge accumulating electrode includes first and second ends, wherein the first thickness and the second thickness form a first junction, and the first thickness and the third thickness form a second junction, and wherein the first junction is located substantially over the first end, and the second junction is located substantially over the second end.